alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame^] | 1 | ; Copyright (c) 2021 Arm Limited. All rights reserved. |
| 2 | ; SPDX-License-Identifier: Apache-2.0 |
| 3 | ; |
| 4 | ; Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | ; you may not use this file except in compliance with the License. |
| 6 | ; You may obtain a copy of the License at |
| 7 | ; |
| 8 | ; http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | ; |
| 10 | ; Unless required by applicable law or agreed to in writing, software |
| 11 | ; distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | ; See the License for the specific language governing permissions and |
| 14 | ; limitations under the License. |
| 15 | |
| 16 | ; ************************************************************* |
| 17 | ; *** Scatter-Loading Description File *** |
| 18 | ; ************************************************************* |
| 19 | ; |
| 20 | ; Sections used: |
| 21 | ;--------------------------------------------------------- |
| 22 | ; | Start | End | Size | Remarks | |
| 23 | ;-|-------------|-------------|-------------|------------| |
| 24 | ; | 0x0000_0000 | 0x0010_0000 | 0x0010_0000 | ITCM (RO) | |
| 25 | ; | 0x0010_0000 | 0x0030_0000 | 0x0020_0000 | BRAM (RW) | |
| 26 | ; | 0x2000_0000 | 0x2040_0000 | 0x0040_0000 | DTCM (RW) | |
| 27 | ; | 0x6000_0000 | 0x6200_0000 | 0x0200_0000 | DRAM (RW) | |
| 28 | ;-|-------------|-------------|-------------|------------| |
| 29 | ; ITCM is aliased at 0x1000_0000 (single bank) |
| 30 | ; BRAM is aliased at 0x1010_0000 |
| 31 | ; DTCM is aliased at 0x3000_0000 (four banks of 1MiB each) |
| 32 | ; DRAM is aliased at 0x7000_0000 (section is 256MiB) |
| 33 | ; |
| 34 | ; Note: Ethos-U55 can only access DRAM and BRAM sections |
| 35 | ;--------------------------------------------------------- |
| 36 | ; First load region |
| 37 | ;--------------------------------------------------------- |
| 38 | LOAD_REGION_0 0x00000000 0x00100000 |
| 39 | { |
| 40 | ;----------------------------------------------------- |
| 41 | ; First part of code mem - 1MiB |
| 42 | ;----------------------------------------------------- |
| 43 | itcm.bin 0x00000000 0x00100000 |
| 44 | { |
| 45 | *.o (RESET, +First) |
| 46 | * (InRoot$$Sections) |
| 47 | .ANY (+RO) |
| 48 | } |
| 49 | |
| 50 | ;----------------------------------------------------- |
| 51 | ; Code memory's 2MiB - reserved for activation buffers |
| 52 | ; Make sure this is uninitialised. |
| 53 | ;----------------------------------------------------- |
| 54 | bram.bin 0x00100000 UNINIT 0x00200000 |
| 55 | { |
| 56 | ; activation buffers a.k.a tensor arena |
| 57 | *.o (.bss.NoInit.activation_buf) |
| 58 | } |
| 59 | |
| 60 | ;----------------------------------------------------- |
| 61 | ; 1MiB bank is used for any other RW or ZI data |
| 62 | ; Note: this region is internal to the Cortex-M CPU |
| 63 | ;----------------------------------------------------- |
| 64 | dtcm.bin 0x20000000 0x00100000 |
| 65 | { |
| 66 | .ANY(+RW +ZI) |
| 67 | } |
| 68 | |
| 69 | ;----------------------------------------------------- |
| 70 | ; 128kiB of stack space within SRAM region |
| 71 | ;----------------------------------------------------- |
| 72 | ARM_LIB_STACK 0x20100000 EMPTY ALIGN 8 0x00020000 |
| 73 | {} |
| 74 | |
| 75 | ;----------------------------------------------------- |
| 76 | ; 2MiB of heap space within the SRAM region |
| 77 | ;----------------------------------------------------- |
| 78 | ARM_LIB_HEAP 0x20200000 EMPTY ALIGN 8 0x00200000 |
| 79 | {} |
| 80 | } |
| 81 | |
| 82 | ;--------------------------------------------------------- |
| 83 | ; Second load region |
| 84 | ;--------------------------------------------------------- |
| 85 | LOAD_REGION_1 0x60000000 0x02000000 |
| 86 | { |
| 87 | ;----------------------------------------------------- |
| 88 | ; 32 MiB of DRAM space for nn model and input vectors |
| 89 | ;----------------------------------------------------- |
| 90 | dram.bin 0x60000000 0x02000000 |
| 91 | { |
| 92 | ; nn model's baked in input matrices |
| 93 | *.o (ifm) |
| 94 | |
| 95 | ; nn model |
| 96 | *.o (nn_model) |
| 97 | |
| 98 | ; if the activation buffer (tensor arena) doesn't |
| 99 | ; fit in the SRAM region, we accommodate it here |
| 100 | *.o (activation_buf) |
| 101 | } |
| 102 | } |