| alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. All rights reserved. |
| 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | // Auto-generated file |
| 18 | // ** DO NOT EDIT ** |
| 19 | |
| 20 | #ifndef PERIPHERAL_MEMMAP_H |
| 21 | #define PERIPHERAL_MEMMAP_H |
| 22 | |
| 23 | #cmakedefine DESIGN_NAME "@DESIGN_NAME@" |
| 24 | |
| 25 | /******************************************************************************/ |
| 26 | /* Peripheral memory map */ |
| 27 | /******************************************************************************/ |
| 28 | |
| 29 | #cmakedefine CMSDK_GPIO0_BASE (@CMSDK_GPIO0_BASE@) /* User GPIO 0 Base Address */ |
| 30 | #cmakedefine CMSDK_GPIO1_BASE (@CMSDK_GPIO1_BASE@) /* User GPIO 1 Base Address */ |
| 31 | #cmakedefine CMSDK_GPIO2_BASE (@CMSDK_GPIO2_BASE@) /* User GPIO 2 Base Address */ |
| 32 | #cmakedefine CMSDK_GPIO3_BASE (@CMSDK_GPIO3_BASE@) /* User GPIO 3 Base Address */ |
| 33 | |
| Liam Barry | 5cdfa9b | 2022-02-02 17:03:06 +0000 | [diff] [blame] | 34 | #cmakedefine FMC_CMDSK_GPIO_BASE0 (@FMC_CMDSK_GPIO_BASE0@) /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */ |
| 35 | #cmakedefine FMC_CMDSK_GPIO_BASE1 (@FMC_CMDSK_GPIO_BASE1@) /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/ |
| 36 | #cmakedefine FMC_CMDSK_GPIO_BASE2 (@FMC_CMDSK_GPIO_BASE2@) /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/ |
| 37 | #cmakedefine FMC_USER_AHB_BASE (@FMC_USER_AHB_BASE@) /* FMC_USER_AHB_BASE Base Address (4KB)*/ |
| alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 38 | |
| 39 | #cmakedefine DMA0_BASE (@DMA0_BASE@) /* DMA0 (4KB) */ |
| 40 | #cmakedefine DMA1_BASE (@DMA1_BASE@) /* DMA1 (4KB) */ |
| 41 | #cmakedefine DMA2_BASE (@DMA2_BASE@) /* DMA2 (4KB) */ |
| 42 | #cmakedefine DMA3_BASE (@DMA3_BASE@) /* DMA3 (4KB) */ |
| 43 | |
| 44 | #cmakedefine USER_APB0_BASE (@USER_APB0_BASE@) /* User APB0 */ |
| 45 | #cmakedefine USER_APB1_BASE (@USER_APB1_BASE@) /* User APB1 */ |
| 46 | #cmakedefine USER_APB2_BASE (@USER_APB2_BASE@) /* User APB2 */ |
| 47 | #cmakedefine USER_APB3_BASE (@USER_APB3_BASE@) /* User APB3 */ |
| 48 | |
| 49 | #cmakedefine MPS3_I2C0_BASE (@MPS3_I2C0_BASE@) /* Touch Screen I2C Base Address */ |
| 50 | #cmakedefine MPS3_I2C1_BASE (@MPS3_I2C1_BASE@) /* Audio Interface I2C Base Address */ |
| 51 | #cmakedefine MPS3_SSP2_BASE (@MPS3_SSP2_BASE@) /* ADC SPI PL022 Base Address */ |
| 52 | #cmakedefine MPS3_SSP3_BASE (@MPS3_SSP3_BASE@) /* Shield 0 SPI PL022 Base Address */ |
| 53 | |
| 54 | #cmakedefine MPS3_SSP4_BASE (@MPS3_SSP4_BASE@) /* Shield 1 SPI PL022 Base Address */ |
| 55 | #cmakedefine MPS3_I2C2_BASE (@MPS3_I2C2_BASE@) /* Shield 0 SBCon Base Address */ |
| 56 | #cmakedefine MPS3_I2C3_BASE (@MPS3_I2C3_BASE@) /* Shield 1 SBCon Base Address */ |
| 57 | |
| 58 | #cmakedefine USER_APB_BASE (@USER_APB_BASE@) /* User APB Base Address */ |
| 59 | #cmakedefine MPS3_I2C4_BASE (@MPS3_I2C4_BASE@) /* HDMI I2C SBCon Base Address */ |
| 60 | #cmakedefine MPS3_I2C5_BASE (@MPS3_I2C5_BASE@) /* DDR EPROM I2C SBCon Base Address */ |
| 61 | #cmakedefine MPS3_SCC_BASE (@MPS3_SCC_BASE@) /* SCC Base Address */ |
| 62 | #cmakedefine MPS3_AAIC_I2S_BASE (@MPS3_AAIC_I2S_BASE@) /* Audio Interface I2S Base Address */ |
| 63 | #cmakedefine MPS3_FPGAIO_BASE (@MPS3_FPGAIO_BASE@) /* FPGA IO Base Address */ |
| 64 | #cmakedefine PL011_UART0_BASE (@PL011_UART0_BASE@) /* PL011 UART0 Base Address */ |
| 65 | #cmakedefine CMSDK_UART0_BASE (@CMSDK_UART0_BASE@) /* UART 0 Base Address */ |
| 66 | #cmakedefine CMSDK_UART1_BASE (@CMSDK_UART1_BASE@) /* UART 1 Base Address */ |
| 67 | #cmakedefine CMSDK_UART2_BASE (@CMSDK_UART2_BASE@) /* UART 2 Base Address */ |
| 68 | #cmakedefine CMSDK_UART3_BASE (@CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/ |
| 69 | |
| Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 70 | #cmakedefine ETHOS_U_NPU_BASE (@ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ |
| 71 | #cmakedefine ETHOS_U_NPU_TA0_BASE (@ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ |
| 72 | #cmakedefine ETHOS_U_NPU_TA1_BASE (@ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ |
| alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 73 | |
| 74 | #cmakedefine CMSDK_UART4_BASE (@CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/ |
| 75 | #cmakedefine CMSDK_UART5_BASE (@CMSDK_UART5_BASE@) /* UART 5 Base Address */ |
| 76 | #cmakedefine HDMI_AUDIO_BASE (@HDMI_AUDIO_BASE@) /* HDMI AUDIO Base Address */ |
| 77 | #cmakedefine CLCD_CONFIG_BASE (@CLCD_CONFIG_BASE@) /* CLCD CONFIG Base Address */ |
| 78 | #cmakedefine RTC_BASE (@RTC_BASE@) /* RTC Base address */ |
| 79 | #cmakedefine SMSC9220_BASE (@SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */ |
| 80 | #cmakedefine USB_BASE (@USB_BASE@) /* USB Base Address */ |
| 81 | #cmakedefine CMSDK_SDIO_BASE (@CMSDK_SDIO_BASE@) /* User SDIO Base Address */ |
| 82 | #cmakedefine MPS3_CLCD_BASE (@MPS3_CLCD_BASE@) /* HDLCD Base Address */ |
| 83 | #cmakedefine MPS3_eMMC_BASE (@MPS3_eMMC_BASE@) /* User eMMC Base Address */ |
| 84 | #cmakedefine USER_BASE (@USER_BASE@) /* User ? Base Address */ |
| 85 | |
| 86 | #cmakedefine QSPI_XIP_BASE (@QSPI_XIP_BASE@) /* QSPI XIP config Base Address */ |
| 87 | #cmakedefine QSPI_WRITE_BASE (@QSPI_WRITE_BASE@) /* QSPI write config Base Address */ |
| 88 | |
| 89 | /******************************************************************************/ |
| 90 | /* Secure Peripheral memory map */ |
| 91 | /******************************************************************************/ |
| 92 | |
| 93 | #cmakedefine MPC_ISRAM0_BASE_S (@MPC_ISRAM0_BASE_S@) /* ISRAM0 Memory Protection Controller Secure base address */ |
| 94 | #cmakedefine MPC_ISRAM1_BASE_S (@MPC_ISRAM1_BASE_S@) /* ISRAM1 Memory Protection Controller Secure base address */ |
| 95 | |
| 96 | #cmakedefine SEC_CMSDK_GPIO0_BASE (@SEC_CMSDK_GPIO0_BASE@) /* User GPIO 0 Base Address */ |
| 97 | #cmakedefine SEC_CMSDK_GPIO1_BASE (@SEC_CMSDK_GPIO1_BASE@) /* User GPIO 0 Base Address */ |
| 98 | #cmakedefine SEC_CMSDK_GPIO2_BASE (@SEC_CMSDK_GPIO2_BASE@) /* User GPIO 0 Base Address */ |
| 99 | #cmakedefine SEC_CMSDK_GPIO3_BASE (@SEC_CMSDK_GPIO3_BASE@) /* User GPIO 0 Base Address */ |
| 100 | |
| 101 | #cmakedefine SEC_AHB_USER0_BASE (@SEC_AHB_USER0_BASE@) /* AHB USER 0 Base Address (4KB) */ |
| 102 | #cmakedefine SEC_AHB_USER1_BASE (@SEC_AHB_USER1_BASE@) /* AHB USER 1 Base Address (4KB)*/ |
| 103 | #cmakedefine SEC_AHB_USER2_BASE (@SEC_AHB_USER2_BASE@) /* AHB USER 2 Base Address (4KB)*/ |
| 104 | #cmakedefine SEC_AHB_USER3_BASE (@SEC_AHB_USER3_BASE@) /* AHB USER 3 Base Address (4KB)*/ |
| 105 | |
| 106 | #cmakedefine SEC_DMA0_BASE (@SEC_DMA0_BASE@) /* DMA0 (4KB) */ |
| 107 | #cmakedefine SEC_DMA1_BASE (@SEC_DMA1_BASE@) /* DMA1 (4KB) */ |
| 108 | #cmakedefine SEC_DMA2_BASE (@SEC_DMA2_BASE@) /* DMA2 (4KB) */ |
| 109 | #cmakedefine SEC_DMA3_BASE (@SEC_DMA3_BASE@) /* DMA3 (4KB) */ |
| 110 | |
| 111 | #cmakedefine SEC_USER_APB0_BASE (@SEC_USER_APB0_BASE@) /* User APB0 */ |
| 112 | #cmakedefine SEC_USER_APB1_BASE (@SEC_USER_APB1_BASE@) /* User APB1 */ |
| 113 | #cmakedefine SEC_USER_APB2_BASE (@SEC_USER_APB2_BASE@) /* User APB2 */ |
| 114 | #cmakedefine SEC_USER_APB3_BASE (@SEC_USER_APB3_BASE@) /* User APB3 */ |
| 115 | |
| 116 | #cmakedefine SEC_MPS3_I2C0_BASE (@SEC_MPS3_I2C0_BASE@) /* Touch Screen I2C Base Address */ |
| 117 | #cmakedefine SEC_MPS3_I2C1_BASE (@SEC_MPS3_I2C1_BASE@) /* Audio Interface I2C Base Address */ |
| 118 | #cmakedefine SEC_MPS3_SSP2_BASE (@SEC_MPS3_SSP2_BASE@) /* ADC SPI PL022 Base Address */ |
| 119 | #cmakedefine SEC_MPS3_SSP3_BASE (@SEC_MPS3_SSP3_BASE@) /* Shield 0 SPI PL022 Base Address */ |
| 120 | |
| 121 | #cmakedefine SEC_MPS3_SSP4_BASE (@SEC_MPS3_SSP4_BASE@) /* Shield 1 SPI PL022 Base Address */ |
| 122 | #cmakedefine SEC_MPS3_I2C2_BASE (@SEC_MPS3_I2C2_BASE@) /* Shield 0 SBCon Base Address */ |
| 123 | #cmakedefine SEC_MPS3_I2C3_BASE (@SEC_MPS3_I2C3_BASE@) /* Shield 1 SBCon Base Address */ |
| 124 | |
| 125 | #cmakedefine SEC_MPS3_I2C4_BASE (@SEC_MPS3_I2C4_BASE@) /* HDMI I2C SBCon Base Address */ |
| 126 | #cmakedefine SEC_MPS3_I2C5_BASE (@SEC_MPS3_I2C5_BASE@) /* DDR EPROM I2C SBCon Base Address */ |
| 127 | #cmakedefine SEC_MPS3_SCC_BASE (@SEC_MPS3_SCC_BASE@) /* SCC Base Address */ |
| 128 | #cmakedefine SEC_MPS3_AAIC_I2S_BASE (@SEC_MPS3_AAIC_I2S_BASE@) /* Audio Interface I2S Base Address */ |
| 129 | #cmakedefine SEC_MPS3_FPGAIO_BASE (@SEC_MPS3_FPGAIO_BASE@) /* FPGA IO Base Address */ |
| 130 | #cmakedefine SEC_CMSDK_UART0_BASE (@SEC_CMSDK_UART0_BASE@) /* UART 0 Base Address */ |
| 131 | #cmakedefine SEC_CMSDK_UART1_BASE (@SEC_CMSDK_UART1_BASE@) /* UART 1 Base Address */ |
| 132 | #cmakedefine SEC_CMSDK_UART2_BASE (@SEC_CMSDK_UART2_BASE@) /* UART 2 Base Address */ |
| 133 | #cmakedefine SEC_CMSDK_UART3_BASE (@SEC_CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/ |
| 134 | |
| 135 | #cmakedefine SEC_CMSDK_UART4_BASE (@SEC_CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/ |
| 136 | #cmakedefine SEC_CMSDK_UART5_BASE (@SEC_CMSDK_UART5_BASE@) /* UART 5 Base Address */ |
| 137 | #cmakedefine SEC_HDMI_AUDIO_BASE (@SEC_HDMI_AUDIO_BASE@) /* HDMI AUDIO Base Address */ |
| 138 | #cmakedefine SEC_CLCD_CONFIG_BASE (@SEC_CLCD_CONFIG_BASE@) /* CLCD CONFIG Base Address */ |
| 139 | #cmakedefine SEC_RTC_BASE (@SEC_RTC_BASE@) /* RTC Base address */ |
| 140 | #cmakedefine SEC_SMSC9220_BASE (@SEC_SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */ |
| 141 | #cmakedefine SEC_USB_BASE (@SEC_USB_BASE@) /* USB Base Address */ |
| 142 | |
| Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 143 | #cmakedefine SEC_ETHOS_U_NPU_BASE (@SEC_ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ |
| 144 | #cmakedefine SEC_ETHOS_U_NPU_TA0_BASE (@SEC_ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ |
| 145 | #cmakedefine SEC_ETHOS_U_NPU_TA1_BASE (@SEC_ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ |
| alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 146 | |
| 147 | #cmakedefine SEC_USER_BASE (@SEC_USER_BASE@) /* User ? Base Address */ |
| 148 | |
| 149 | #cmakedefine SEC_QSPI_XIP_BASE (@SEC_QSPI_XIP_BASE@) /* QSPI XIP config Base Address */ |
| 150 | #cmakedefine SEC_QSPI_WRITE_BASE (@SEC_QSPI_WRITE_BASE@) /* QSPI write config Base Address */ |
| 151 | |
| 152 | /******************************************************************************/ |
| 153 | /* MPCs */ |
| 154 | /******************************************************************************/ |
| 155 | |
| 156 | #cmakedefine MPC_ISRAM0_BASE_S (@MPC_ISRAM0_BASE_S@) /* Internal SRAM 0 MPC */ |
| 157 | #cmakedefine MPC_ISRAM1_BASE_S (@MPC_ISRAM1_BASE_S@) /* Internal SRAM 1 MPC */ |
| 158 | #cmakedefine MPC_BRAM_BASE_S (@MPC_BRAM_BASE_S@) /* SRAM Memory Protection Controller Secure base address */ |
| 159 | #cmakedefine MPC_QSPI_BASE_S (@MPC_QSPI_BASE_S@) /* QSPI Memory Protection Controller Secure base address */ |
| 160 | #cmakedefine MPC_DDR4_BASE_S (@MPC_DDR4_BASE_S@) /* DDR4 Memory Protection Controller Secure base address */ |
| 161 | |
| 162 | #endif /* PERIPHERAL_MEMMAP_H */ |