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alexander3c798932021-03-26 21:42:19 +00001#----------------------------------------------------------------------------
2# Copyright (c) 2021 Arm Limited. All rights reserved.
3# SPDX-License-Identifier: Apache-2.0
4#
5# Licensed under the Apache License, Version 2.0 (the "License");
6# you may not use this file except in compliance with the License.
7# You may obtain a copy of the License at
8#
9# http://www.apache.org/licenses/LICENSE-2.0
10#
11# Unless required by applicable law or agreed to in writing, software
12# distributed under the License is distributed on an "AS IS" BASIS,
13# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14# See the License for the specific language governing permissions and
15# limitations under the License.
16#----------------------------------------------------------------------------
17set(CMAKE_INSTALL_PREFIX ${CMAKE_SOURCE_DIR}/build_baremetal)
18set(PLAT_HAL ${CMAKE_CURRENT_SOURCE_DIR}/source/application/hal/platforms/bare-metal)
19
20# If target platform not defined raise an error
21# TARGET_PLATFORM either should have been defined by the user or set to default value mps3
22if (NOT DEFINED TARGET_PLATFORM)
23 message(FATAL_ERROR "Invalid target platform, specify TARGET_PLATFORM=mps3")
24endif ()
25message(STATUS "target platform ${TARGET_PLATFORM}")
26
27set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp)
28if (NOT DEFINED MEM_PROFILES_SRC_DIR)
29 set(MEM_PROFILES_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/subsystem-profiles)
30endif()
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010031
alexander3c798932021-03-26 21:42:19 +000032set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/peripheral_memmap.h.template)
33set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/peripheral_irqs.h.template)
34set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/mem_regions.h.template)
35set(TA_SETTINGS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/timing_adapter_settings.template)
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010036set(LINKER_SCRIPT_DIR "${PLAT_HAL}/bsp/mem_layout")
alexander3c798932021-03-26 21:42:19 +000037set(TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME "libtensorflow-microlite.a")
38set(TENSORFLOW_LITE_MICRO_FLAG "-DTF_LITE_STATIC_MEMORY")
Cisco Cervelleraf085fa52021-08-02 09:32:07 +010039set(ETHOS_U_NPU_FLAG "-DARM_NPU=1")
alexander3c798932021-03-26 21:42:19 +000040
Cisco Cervelleraf085fa52021-08-02 09:32:07 +010041if (ETHOS_U_NPU_ENABLED)
42 set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} ${ETHOS_U_NPU_FLAG}")
alexander3c798932021-03-26 21:42:19 +000043endif ()
44
45# Set specific flags depending on target platform and subsystem
46if (TARGET_PLATFORM STREQUAL mps3)
47 set(MPS3_PLATFORM_FLAG "-DMPS3_PLATFORM=1")
48
49 # If target platform is mps3 and subsystem not defined raise an error,
50 # TARGET_SUBSYSTEM either should have been defined by the user or set to a default value
51 if (NOT DEFINED TARGET_SUBSYSTEM)
52 message(FATAL_ERROR "Target subsystem for mps3 undefined, "
alexanderd580eee2021-05-04 21:24:22 +010053 "specify -DTARGET_SUBSYSTEM=<sse-300>")
alexander3c798932021-03-26 21:42:19 +000054 endif ()
55
alexanderd580eee2021-05-04 21:24:22 +010056 if (TARGET_SUBSYSTEM STREQUAL sse-300)
alexander3c798932021-03-26 21:42:19 +000057 message(STATUS "target subsystem is ${TARGET_SUBSYSTEM}")
58 set(BSP_PACKAGE_DIR "${PLAT_HAL}/bsp/bsp-packs/mps3")
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010059 set(LINKER_SCRIPT_NAME "${TARGET_PLATFORM}-${TARGET_SUBSYSTEM}")
alexander3c798932021-03-26 21:42:19 +000060
61 # Include the mem profile definitions specific to our target subsystem
62 include(${MEM_PROFILES_SRC_DIR}/corstone-${TARGET_SUBSYSTEM}.cmake)
63 set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} ${MPS3_PLATFORM_FLAG}")
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010064
65 # For deployment on the MPS3 FPGA platform, we need to produce
66 # two bin files - one that is loaded into the ITCM, and another
67 # that is loaded into the DDR region.
Kshitij Sisodia69a47452021-07-23 17:43:54 +010068 set(LINKER_SECTION_TAGS "*.at_itcm" "*.at_ddr")
69 set(LINKER_OUTPUT_BIN_TAGS "itcm.bin" "ddr.bin")
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010070 set(MPS3_FPGA_CONFIG "${CMAKE_CURRENT_SOURCE_DIR}/scripts/${TARGET_PLATFORM}/${TARGET_SUBSYSTEM}/images.txt")
alexander3c798932021-03-26 21:42:19 +000071 else ()
72 message(FATAL_ERROR "Non compatible target subsystem: ${TARGET_SUBSYSTEM}")
73 endif ()
74elseif (TARGET_PLATFORM STREQUAL simple_platform)
Kshitij Sisodia69a47452021-07-23 17:43:54 +010075 set(BSP_PACKAGE_DIR "${PLAT_HAL}/bsp/bsp-packs/${TARGET_PLATFORM}")
76 set(LINKER_SCRIPT_NAME "${TARGET_PLATFORM}")
alexander3c798932021-03-26 21:42:19 +000077 include(${MEM_PROFILES_SRC_DIR}/${TARGET_PLATFORM}.cmake)
Kshitij Sisodia69a47452021-07-23 17:43:54 +010078 set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS}")
79 set(LINKER_SECTION_TAGS "*.at_itcm" "*.at_ddr")
80 set(LINKER_OUTPUT_BIN_TAGS "itcm.bin" "ddr.bin")
alexander3c798932021-03-26 21:42:19 +000081else ()
82 message(FATAL_ERROR "Non compatible target platform ${TARGET_PLATFORM}")
83endif ()
84
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010085# Add link options for the linker script to be used:
86add_linker_script(${LINKER_SCRIPT_DIR} ${LINKER_SCRIPT_NAME})
87
Cisco Cervelleraf085fa52021-08-02 09:32:07 +010088if (ETHOS_U_NPU_ENABLED)
alexander3c798932021-03-26 21:42:19 +000089 USER_OPTION(TA_CONFIG_FILE "Path to the timing adapter configuration file"
Cisco Cervelleraf085fa52021-08-02 09:32:07 +010090 "${CMAKE_SCRIPTS_DIR}/timing_adapter/ta_config_u55_high_end.cmake"
alexander3c798932021-03-26 21:42:19 +000091 FILEPATH)
92
93 # must be included after target subsystem CMake file
94 include(${TA_CONFIG_FILE})
95endif()
96
97# Generate the memory map header file from the mem profile cmake included in one of
98# the previous sections
99message(STATUS "Configuring file from ${MEM_PROFILE_TEMPLATE}"
100 ", ${IRQ_PROFILE_TEMPLATE}"
101 " and ${MEM_REGIONS_TEMPLATE}")
102
103configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h")
104configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h")
105configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h")
106configure_file("${TA_SETTINGS_TEMPLATE}" "${SOURCE_GEN_DIR}/timing_adapter_settings.h")
107
alexander3c798932021-03-26 21:42:19 +0000108message(STATUS "Using BSP package from: ${BSP_PACKAGE_DIR}")
109
110if (DEFINED VERIFY_TEST_OUTPUT)
111 message(STATUS "Test output verification flag is: ${VERIFY_TEST_OUTPUT}")
112 set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DVERIFY_TEST_OUTPUT=${VERIFY_TEST_OUTPUT}")
113endif ()
114
115if (DEFINED LOG_LEVEL)
116 message(STATUS "Setting log level to ${LOG_LEVEL}")
117 set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DLOG_LEVEL=${LOG_LEVEL}")
118endif()
119
120if (DEFINED ACTIVATION_BUF_SRAM_SZ)
121 message(STATUS "Maximum SRAM space for activations buffers for this system: ${ACTIVATION_BUF_SRAM_SZ}")
122 set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ}")
123endif()
124
125if (DEFINED ARMCLANG_DEBUG_DWARF_LEVEL)
126 message(STATUS "setting dwarf conformance level to gdwarf-${ARMCLANG_DEBUG_DWARF_LEVEL}")
127 set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -gdwarf-${ARMCLANG_DEBUG_DWARF_LEVEL}")
128endif()
129
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +0100130set(COMPILER_FLAGS "${TENSORFLOW_LITE_MICRO_FLAG} ${PROFILING_OPT} ${OPTIONAL_FLAGS}")
alexander3c798932021-03-26 21:42:19 +0000131# For some reason, cmake doesn't pass the c++ standard flag, adding it manually
132set(CMAKE_CXX_FLAGS "${COMPILER_FLAGS} -std=c++11" CACHE INTERNAL "")
133set(CMAKE_C_FLAGS "${COMPILER_FLAGS}" CACHE INTERNAL "")
alexander3c798932021-03-26 21:42:19 +0000134set(CMAKE_ASM_COMPILE_OBJECT ${CMAKE_CXX_FLAGS})
135
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +0100136# Tell linker that reset interrupt handler is our entry point
137add_link_options(--entry Reset_Handler)
alexander3c798932021-03-26 21:42:19 +0000138
139set(PLAT_BSP_INCLUDES
140 ${PLAT_HAL}/bsp/cmsis-device/include
141 ${PLAT_HAL}/bsp/include/
142 ${PLAT_HAL}/bsp/bsp-core/include
143 ${BSP_PACKAGE_DIR}/include
144)
145
146# Include directories:
147set(PLAT_INCLUDE_DIRS
148 ${PLAT_BSP_INCLUDES}
149 ${PLAT_HAL}/utils/include
150 ${PLAT_HAL}/images/include
151 ${PLAT_HAL}/data_presentation/lcd/include
152 ${PLAT_HAL}/timer/include
153 ${SOURCE_GEN_DIR}
154 )
155
156# Source files
157file(GLOB_RECURSE SRC_PLAT_HAL
158
159 # Higher level HAL sources - software logic implementations
160 "${PLAT_HAL}/data_*/*.c"
161 "${PLAT_HAL}/images/*.c"
162 "${PLAT_HAL}/timer/*.c"
163 "${PLAT_HAL}/utils/*.c"
164
165 # Low level HAL sources - these enable interaction with
166 # the actual hardware
167 "${PLAT_HAL}/bsp/cmsis-device/*.c"
168 "${PLAT_HAL}/bsp/bsp-core/*.c"
169 "${BSP_PACKAGE_DIR}/*.c"
170 )
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +0100171
172# Special retarget source to direct stdin, stdout and stderr streams to the
173# UART block.
174set(PLAT_RETARGET_SOURCE "${PLAT_HAL}/bsp/bsp-core/retarget.c")