blob: 7040cf382309549a06e6e85d5355086dd3fdaa2a [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +00001/*
2 * Copyright (c) 2021 Arm Limited. All rights reserved.
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17#include "device_mps3.h"
18
19#include "bsp_core_log.h"
20#include "smm_mps3.h"
21
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010022#include <inttypes.h>
23
alexander3c798932021-03-26 21:42:19 +000024uint32_t GetMPS3CoreClock(void)
25{
26 const uint32_t default_clock = 32000000;
27 static int warned_once = 0;
28 if (0 != MPS3_SCC->CFG_ACLK) {
29 return MPS3_SCC->CFG_ACLK;
30 }
31
32 if (!warned_once) {
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010033 warn("MPS3_SCC->CFG_ACLK reads 0. Assuming default clock of %" PRIu32 "\n",
alexander3c798932021-03-26 21:42:19 +000034 default_clock);
35 warned_once = 1;
36 }
37 return default_clock;
38}