Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022 Arm Limited. |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to |
| 8 | * deal in the Software without restriction, including without limitation the |
| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in all |
| 14 | * copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 22 | * SOFTWARE. |
| 23 | */ |
| 24 | #include "src/runtime/heuristics/indirect_conv/ClIndirectConvDefaultConfigValhall.h" |
| 25 | |
| 26 | #include "arm_compute/core/CL/CLHelpers.h" |
| 27 | #include "arm_compute/core/GPUTarget.h" |
| 28 | #include "arm_compute/core/TensorInfo.h" |
| 29 | #include "arm_compute/core/TensorShape.h" |
| 30 | #include "arm_compute/core/utils/misc/ShapeCalculator.h" |
| 31 | |
| 32 | namespace arm_compute |
| 33 | { |
| 34 | namespace cl_indirect_conv |
| 35 | { |
| 36 | using namespace arm_compute::misc::shape_calculator; |
| 37 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 38 | ClIndirectConvDefaultConfigValhall::ClIndirectConvDefaultConfigValhall(GPUTarget gpu) : IClIndirectConvKernelConfig(gpu) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 39 | { |
| 40 | } |
| 41 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 42 | DirectConvComputeKernelInfo ClIndirectConvDefaultConfigValhall::configure(const ITensorInfo *src, |
| 43 | const ITensorInfo *wei, |
| 44 | const PadStrideInfo &conv_info) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 45 | { |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 46 | using ConfigurationFunctionExecutorPtr = DirectConvComputeKernelInfo (ClIndirectConvDefaultConfigValhall::*)( |
| 47 | const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 48 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 49 | ClIndirectConvConfigArray<ConfigurationFunctionExecutorPtr> configs_G77( |
| 50 | &ClIndirectConvDefaultConfigValhall::configure_G77_f32, &ClIndirectConvDefaultConfigValhall::configure_G77_f16); |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 51 | |
| 52 | // Important note: Indirect convolution should not be used when the kernel size is 1x1 (pointwise). The reason is because the indirect buffer makes |
| 53 | // indirect convolution less efficient than direct convolution or gemm. For this reason, the heuristic of indirect convolution has not been tuned |
| 54 | // for the pointwise convolution cases. |
| 55 | |
| 56 | ConfigurationFunctionExecutorPtr func = configs_G77.get_function(src->data_type()); |
| 57 | |
| 58 | ARM_COMPUTE_ERROR_ON_MSG(func == nullptr, "Data type not supported for indirect convolution"); |
| 59 | return (this->*func)(src, wei, conv_info); |
| 60 | } |
| 61 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 62 | DirectConvComputeKernelInfo ClIndirectConvDefaultConfigValhall::configure_G77_f32(const ITensorInfo *src, |
| 63 | const ITensorInfo *wei, |
| 64 | const PadStrideInfo &conv_info) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 65 | { |
| 66 | DirectConvComputeKernelInfo desc; |
| 67 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 68 | if (src->data_layout() == DataLayout::NHWC) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 69 | { |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 70 | const TensorShape dst_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 71 | const bool export_weights_to_cl_image = export_to_cl_image(wei); |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 72 | const int32_t stride_x = conv_info.stride().first; |
| 73 | const int32_t stride_y = conv_info.stride().second; |
| 74 | const int32_t ofm = dst_shape[0]; |
| 75 | const int32_t m = (dst_shape[1] / stride_x) * (dst_shape[2] / stride_y); |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 76 | |
| 77 | desc.export_weights_to_cl_image = export_weights_to_cl_image; |
| 78 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 79 | if (ofm <= 4) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 80 | { |
| 81 | desc.m0 = 1; |
| 82 | desc.n0 = 2; |
| 83 | desc.k0 = 16; |
| 84 | } |
| 85 | else |
| 86 | { |
| 87 | // The 16000 threshold value has been identified as the right |
| 88 | // one for using the biggest block size allowed on F32: 5x4x4 |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 89 | if (m < 16000) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 90 | { |
| 91 | desc.m0 = 4; |
| 92 | desc.n0 = 4; |
| 93 | desc.k0 = 4; |
| 94 | } |
| 95 | else |
| 96 | { |
| 97 | desc.m0 = 5; |
| 98 | desc.n0 = 4; |
| 99 | desc.k0 = 4; |
| 100 | } |
| 101 | } |
| 102 | } |
| 103 | |
| 104 | return desc; |
| 105 | } |
| 106 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 107 | DirectConvComputeKernelInfo ClIndirectConvDefaultConfigValhall::configure_G77_f16(const ITensorInfo *src, |
| 108 | const ITensorInfo *wei, |
| 109 | const PadStrideInfo &conv_info) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 110 | { |
| 111 | DirectConvComputeKernelInfo desc; |
| 112 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 113 | if (src->data_layout() == DataLayout::NHWC) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 114 | { |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 115 | const TensorShape wei_shape = wei->tensor_shape(); |
| 116 | const TensorShape dst_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 117 | const bool export_weights_to_cl_image = export_to_cl_image(wei); |
| 118 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 119 | const int32_t ofm = dst_shape[0]; |
| 120 | const int32_t m = dst_shape[1] * dst_shape[2]; |
| 121 | const int32_t k = wei_shape[0]; |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 122 | |
| 123 | desc.export_weights_to_cl_image = export_weights_to_cl_image; |
| 124 | |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 125 | if (ofm <= 4) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 126 | { |
| 127 | // k0 should be as larger as possible. However, we should avoid |
| 128 | // having left-over for loops that make the implementation slower. |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 129 | if ((k % 16) == 0) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 130 | { |
| 131 | desc.k0 = 16; |
| 132 | } |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 133 | else if ((k % 8) == 0) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 134 | { |
| 135 | desc.k0 = 8; |
| 136 | } |
| 137 | else |
| 138 | { |
| 139 | desc.k0 = 4; |
| 140 | } |
| 141 | |
| 142 | desc.m0 = 1; |
| 143 | desc.n0 = ofm; |
| 144 | } |
| 145 | else |
| 146 | { |
| 147 | // The 16000 threshold value has been identified as the right |
| 148 | // one for using the biggest block size allowed on F16: 8x4 |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 149 | if (m >= 16000 && k < 4) |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 150 | { |
| 151 | desc.m0 = 8; |
| 152 | desc.n0 = 4; |
Felix Thomasmathibalan | afd38f0 | 2023-09-27 17:46:17 +0100 | [diff] [blame] | 153 | desc.k0 = 4; // k0 is clamped to k inside the kernel when k is less than 4 |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 154 | } |
| 155 | else |
| 156 | { |
| 157 | desc.m0 = 5; |
| 158 | desc.n0 = 4; |
| 159 | desc.k0 = 8; |
| 160 | } |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | return desc; |
| 165 | } |
Gian Marco Iodice | 9d3bd41 | 2022-12-30 09:45:00 +0000 | [diff] [blame] | 166 | } // namespace cl_indirect_conv |
Gian Marco Iodice | a5cb79f | 2022-12-28 13:53:51 +0000 | [diff] [blame] | 167 | } // namespace arm_compute |