Blame - src/core/NEON/kernels/assembly/NEPoolingAssemblyWrapperKernel.cpp - ml/ComputeLibrary

ARM_COMPUTE_RETURN_ERROR_ON_MSG((input->data_layout() != DataLayout::NHWC) || (info.data_layout != DataLayout::NHWC), "Only NHWC is supported by assembly kernels");

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ARM_COMPUTE_RETURN_ERROR_ON_MSG((info.pool_type != PoolingType::AVG) && (info.pool_type != PoolingType::MAX),

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"Only AVG and MAX pooling are supported by assembly kernels");

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if(output->total_size() > 0)

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{

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ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(input, output);

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const auto input_qinfo = input->quantization_info().uniform();

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const auto output_qinfo = output->quantization_info().uniform();

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if(input_qinfo != output_qinfo)

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{

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const float multiplier = input_qinfo.scale / output_qinfo.scale;

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int32_t output_multiplier{};

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int32_t output_shift{};

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ARM_COMPUTE_RETURN_ERROR_ON(quantization::calculate_quantized_multiplier(multiplier, &output_multiplier, &output_shift));

}

else

{

if(input->data_type() == DataType::QASYMM8)

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{

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const bool has_padding = info.pad_stride_info.has_padding();

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ARM_COMPUTE_RETURN_ERROR_ON_MSG(!info.exclude_padding && has_padding, "Assembly kernels do not support padding for QASYMM8 with same input/output quantization info");

}

}

}

else

{

if(input->data_type() == DataType::QASYMM8)

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{

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// If output is not configured, the quantization info are the same

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const bool has_padding = info.pad_stride_info.has_padding();

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ARM_COMPUTE_RETURN_ERROR_ON_MSG(!info.exclude_padding && has_padding, "Assembly kernels do not support padding for QASYMM8 with same input/output quantization info");

}

}

return Status{};

}

void NEPoolingAssemblyWrapperKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)

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{

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ARM_COMPUTE_ERROR_ON_NULLPTR(_kernel_asm.get());

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ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this);

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ARM_COMPUTE_UNUSED(window);

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ARM_COMPUTE_UNUSED(info);

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ARM_COMPUTE_ERROR_ON(tensors.empty());

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const ITensor *input = tensors.get_const_tensor(TensorType::ACL_SRC);

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ITensor *output = tensors.get_tensor(TensorType::ACL_DST_0);

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ITensor *workspace = tensors.get_tensor(TensorType::ACL_DST_1);

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const auto in_ptr = input->buffer() + input->info()->offset_first_element_in_bytes();

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auto out_ptr = output->buffer() + output->info()->offset_first_element_in_bytes();

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auto working_space = workspace->buffer() + workspace->info()->offset_first_element_in_bytes();

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Michele Di Giorgio

74a142c

2021-02-02 10:54:26 +0000

[diff] [blame]

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const auto input_shape = input->info()->tensor_shape();

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const auto output_shape = output->info()->tensor_shape();

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const auto input_padding = input->info()->padding();

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const auto output_padding = output->info()->padding();

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const size_t ld_input_col = input_shape[0] + input_padding.left + input_padding.right;

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const size_t ld_input_row = ld_input_col * (input_shape[1] + input_padding.top + input_padding.bottom);

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const size_t ld_input_batch = ld_input_row * input_shape[2];

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const size_t ld_output_col = output_shape[0] + output_padding.right;

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const size_t ld_output_row = ld_output_col * (output_shape[1] + output_padding.top + output_padding.bottom);

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const size_t ld_output_batch = ld_output_row * output_shape[2];

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_kernel_asm->execute(in_ptr, ld_input_col, ld_input_row, ld_input_batch,

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out_ptr, ld_output_col, ld_output_row, ld_output_batch,

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working_space, info.thread_id, info.num_threads);

Michele Di Giorgio

d556d7b

2020-10-27 10:56:31 +0000

[diff] [blame]

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}

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size_t NEPoolingAssemblyWrapperKernel::get_working_size(unsigned int num_threads) const

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{

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return _kernel_asm->get_working_size(num_threads);

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}

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bool NEPoolingAssemblyWrapperKernel::is_configured() const

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{

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return _kernel_asm != nullptr;

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}

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template <typename TypeInput, typename TypeOutput>

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void NEPoolingAssemblyWrapperKernel::create_arm_pooling(const ITensorInfo *input, ITensorInfo *output, const PoolingLayerInfo &info, const CPUInfo &cpu_info)

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{

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const arm_conv::pooling::PoolingType pool_type = (info.pool_type == PoolingType::AVG) ? arm_conv::pooling::PoolingType::AVERAGE : arm_conv::pooling::PoolingType::MAX;

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arm_conv::pooling::PoolingWindow window{};

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window.cols = static_cast<unsigned int>(info.pool_size.x());

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window.rows = static_cast<unsigned int>(info.pool_size.y());

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arm_conv::pooling::PoolingStride stride{};

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std::tie(stride.cols, stride.rows) = info.pad_stride_info.stride();

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const arm_conv::pooling::PaddingValues padding{ info.pad_stride_info.pad_left(), info.pad_stride_info.pad_top(), info.pad_stride_info.pad_right(), info.pad_stride_info.pad_bottom() };

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constexpr unsigned int idx_width = 1;

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constexpr unsigned int idx_height = 2;

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constexpr unsigned int idx_channels = 0;

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constexpr unsigned int idx_batches = 3;

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const unsigned int n_batches = input->dimension(idx_batches);

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const unsigned int input_rows = input->dimension(idx_height);

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const unsigned int input_cols = input->dimension(idx_width);

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const unsigned int n_channels = input->dimension(idx_channels);

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const unsigned int output_rows = output->dimension(idx_height);

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const unsigned int output_cols = output->dimension(idx_width);

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arm_conv::pooling::PoolingArgs args(&cpu_info, pool_type, window, stride, info.exclude_padding, n_batches, input_rows, input_cols, n_channels, output_rows, output_cols, padding, nullptr);

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// Configure assembly pooling kernel

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auto pooling_kernel_asm = arm_conv::pooling::pooling<TypeInput, TypeOutput>(args);

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if(pooling_kernel_asm == nullptr)

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{

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// Configuration not supported: Leave function unconfigured:

return;

}

_kernel_asm = std::move(pooling_kernel_asm);

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}

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