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telsoa014fcda012018-03-09 14:13:49 +00001//
2// Copyright © 2017 Arm Ltd. All rights reserved.
David Beckecb56cd2018-09-05 12:52:57 +01003// SPDX-License-Identifier: MIT
telsoa014fcda012018-03-09 14:13:49 +00004//
5#pragma once
6
Aron Virginas-Tarc9cc8042018-11-01 16:15:57 +00007#include "CpuTensorHandleFwd.hpp"
telsoa014fcda012018-03-09 14:13:49 +00008#include "WorkloadDataFwd.hpp"
9
Aron Virginas-Tarc9cc8042018-11-01 16:15:57 +000010#include <InternalTypes.hpp>
11
David Beck0dbe0ee2018-09-24 15:59:27 +010012#include <armnn/Descriptors.hpp>
13#include <armnn/Exceptions.hpp>
Aron Virginas-Tarc9cc8042018-11-01 16:15:57 +000014#include <armnn/Types.hpp>
15#include <armnn/Tensor.hpp>
David Beck0dbe0ee2018-09-24 15:59:27 +010016
Aron Virginas-Tarc9cc8042018-11-01 16:15:57 +000017#include <backendsCommon/OutputHandler.hpp>
18#include <backendsCommon/WorkloadInfo.hpp>
telsoa014fcda012018-03-09 14:13:49 +000019
20namespace armnn
21{
22
telsoa01c577f2c2018-08-31 09:22:23 +010023//A helper function that returns the bias data type required for given input data type.
telsoa014fcda012018-03-09 14:13:49 +000024DataType GetBiasDataType(DataType inputDataType);
25
26struct WorkloadInfo;
27
28struct QueueDescriptor
29{
30 std::vector<ITensorHandle*> m_Inputs;
31 std::vector<ITensorHandle*> m_Outputs;
32
33 void ValidateInputsOutputs(const std::string& descName,
34 unsigned int numExpectedIn, unsigned int numExpectedOut) const;
35
36
37protected:
38 ~QueueDescriptor() = default;
39 QueueDescriptor() = default;
40 QueueDescriptor(QueueDescriptor const&) = default;
41 QueueDescriptor& operator=(QueueDescriptor const&) = default;
42};
43
telsoa01c577f2c2018-08-31 09:22:23 +010044// Base class for queue descriptors which contain parameters.
telsoa014fcda012018-03-09 14:13:49 +000045template <typename LayerDescriptor>
46struct QueueDescriptorWithParameters : public QueueDescriptor
47{
48 LayerDescriptor m_Parameters;
49
50protected:
51 ~QueueDescriptorWithParameters() = default;
52 QueueDescriptorWithParameters() = default;
53 QueueDescriptorWithParameters(QueueDescriptorWithParameters const&) = default;
54 QueueDescriptorWithParameters& operator=(QueueDescriptorWithParameters const&) = default;
55};
56
57struct MemCopyQueueDescriptor : QueueDescriptor
58{
59 void Validate(const WorkloadInfo& workloadInfo) const;
60};
61
62using InputQueueDescriptor = MemCopyQueueDescriptor;
63using OutputQueueDescriptor = MemCopyQueueDescriptor;
64
telsoa01c577f2c2018-08-31 09:22:23 +010065// Softmax layer workload data.
telsoa014fcda012018-03-09 14:13:49 +000066struct SoftmaxQueueDescriptor : QueueDescriptorWithParameters<SoftmaxDescriptor>
67{
68 void Validate(const WorkloadInfo& workloadInfo) const;
69};
70
telsoa01c577f2c2018-08-31 09:22:23 +010071// Splitter layer workload data.
telsoa014fcda012018-03-09 14:13:49 +000072struct SplitterQueueDescriptor : QueueDescriptorWithParameters<ViewsDescriptor>
73{
74 struct ViewOrigin
75 {
76 ViewOrigin() {}
77 ViewOrigin(std::vector<unsigned int> const& origin) : m_Origin(origin) {}
78
telsoa01c577f2c2018-08-31 09:22:23 +010079 //View origin (size of the vector is the same as number of dimensions of the view).
telsoa014fcda012018-03-09 14:13:49 +000080 std::vector<unsigned int> m_Origin;
81 };
82
telsoa01c577f2c2018-08-31 09:22:23 +010083 //View defines a tensor that will be carved from the input tensor.
84 //View origins are stored here, the extents are defined by sizes of the output tensors.
telsoa014fcda012018-03-09 14:13:49 +000085 std::vector<ViewOrigin> m_ViewOrigins;
86
87 void Validate(const WorkloadInfo& workloadInfo) const;
88};
89
telsoa01c577f2c2018-08-31 09:22:23 +010090// Merger layer workload data.
telsoa014fcda012018-03-09 14:13:49 +000091struct MergerQueueDescriptor : QueueDescriptorWithParameters<OriginsDescriptor>
92{
93 struct ViewOrigin
94 {
95 ViewOrigin() {}
96 ViewOrigin(const std::vector<unsigned int>& origin) : m_Origin(origin) {}
97
telsoa01c577f2c2018-08-31 09:22:23 +010098 //View origin (size of the vector is the same as number of dimensions of the view).
telsoa014fcda012018-03-09 14:13:49 +000099 std::vector<unsigned int> m_Origin;
100 };
101
telsoa01c577f2c2018-08-31 09:22:23 +0100102 //View defines a sub-area of the output tensor that will be filled with the corresponding input tensor.
103 //View origins are stored here, the extents are defined by sizes of the input tensors.
telsoa014fcda012018-03-09 14:13:49 +0000104 std::vector<ViewOrigin> m_ViewOrigins;
105
106 void Validate(const WorkloadInfo& workloadInfo) const;
107};
108
telsoa01c577f2c2018-08-31 09:22:23 +0100109// Activation layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000110struct ActivationQueueDescriptor : QueueDescriptorWithParameters<ActivationDescriptor>
111{
112 void Validate(const WorkloadInfo& workloadInfo) const;
113};
114
telsoa01c577f2c2018-08-31 09:22:23 +0100115// Fully connected layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000116struct FullyConnectedQueueDescriptor : QueueDescriptorWithParameters<FullyConnectedDescriptor>
117{
118 FullyConnectedQueueDescriptor()
119 : m_Weight(nullptr)
120 , m_Bias(nullptr)
121 {
122 }
123
124 const ConstCpuTensorHandle* m_Weight;
125 const ConstCpuTensorHandle* m_Bias;
126
127 void Validate(const WorkloadInfo& workloadInfo) const;
128};
129
telsoa01c577f2c2018-08-31 09:22:23 +0100130// Permute layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000131struct PermuteQueueDescriptor : QueueDescriptorWithParameters<PermuteDescriptor>
132{
133 void Validate(const WorkloadInfo& workloadInfo) const;
134};
135
telsoa01c577f2c2018-08-31 09:22:23 +0100136// Pooling 2D layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000137struct Pooling2dQueueDescriptor : QueueDescriptorWithParameters<Pooling2dDescriptor>
138{
139 void Validate(const WorkloadInfo& workloadInfo) const;
140};
141
telsoa01c577f2c2018-08-31 09:22:23 +0100142// Convolution 2D layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000143struct Convolution2dQueueDescriptor : QueueDescriptorWithParameters<Convolution2dDescriptor>
144{
145 Convolution2dQueueDescriptor()
146 : m_Weight(nullptr)
147 , m_Bias(nullptr)
148 {
149 }
150
151 const ConstCpuTensorHandle* m_Weight;
152 const ConstCpuTensorHandle* m_Bias;
153
154 void Validate(const WorkloadInfo& workloadInfo) const;
155};
156
telsoa01c577f2c2018-08-31 09:22:23 +0100157// Depthwise Convolution 2D layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000158struct DepthwiseConvolution2dQueueDescriptor : QueueDescriptorWithParameters<DepthwiseConvolution2dDescriptor>
159{
160 DepthwiseConvolution2dQueueDescriptor()
161 : m_Weight(nullptr)
162 , m_Bias(nullptr)
163 {
164 }
165
166 const ConstCpuTensorHandle* m_Weight;
167 const ConstCpuTensorHandle* m_Bias;
168
169 void Validate(const WorkloadInfo& workloadInfo) const;
170};
171
telsoa01c577f2c2018-08-31 09:22:23 +0100172// Normalization layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000173struct NormalizationQueueDescriptor : QueueDescriptorWithParameters<NormalizationDescriptor>
174{
175 void Validate(const WorkloadInfo& workloadInfo) const;
176};
177
telsoa01c577f2c2018-08-31 09:22:23 +0100178// Add layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000179struct AdditionQueueDescriptor : QueueDescriptor
180{
181 void Validate(const WorkloadInfo& workloadInfo) const;
182};
183
telsoa01c577f2c2018-08-31 09:22:23 +0100184// Multiplication layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000185struct MultiplicationQueueDescriptor : QueueDescriptor
186{
187 void Validate(const WorkloadInfo& workloadInfo) const;
188};
189
Francis Murtaghe7a86a42018-08-29 12:42:10 +0100190// Division layer workload data.
191struct DivisionQueueDescriptor : QueueDescriptor
192{
193 void Validate(const WorkloadInfo& workloadInfo) const;
194};
195
David Beckc2044fe2018-09-05 15:00:38 +0100196// Subtraction layer workload data.
197struct SubtractionQueueDescriptor : QueueDescriptor
198{
199 void Validate(const WorkloadInfo& workloadInfo) const;
200};
201
Nattapat Chaimanowong5a4304a2018-11-28 10:44:37 +0000202// Maximum layer workload data.
203struct MaximumQueueDescriptor : QueueDescriptor
204{
205 void Validate(const WorkloadInfo& workloadInfo) const;
206};
207
narpra01a6bf9122018-09-10 09:50:09 +0100208// Mean layer workload data.
narpra0132b90462018-09-13 11:07:48 +0100209struct MeanQueueDescriptor : QueueDescriptorWithParameters<MeanDescriptor>
narpra01a6bf9122018-09-10 09:50:09 +0100210{
211 void Validate(const WorkloadInfo& workloadInfo) const;
212};
213
jimfly012c9322a2018-09-19 10:59:49 +0100214// Pad layer workload data
215struct PadQueueDescriptor : QueueDescriptorWithParameters<PadDescriptor>
216{
217 void Validate(const WorkloadInfo& workloadInfo) const;
218};
219
FrancisMurtagh20995952018-12-17 12:11:36 +0000220// Equal layer workload data
221struct EqualQueueDescriptor : QueueDescriptor
222{
223 void Validate(const WorkloadInfo& workloadInfo) const;
224};
225
telsoa01c577f2c2018-08-31 09:22:23 +0100226// Batch norm layer workload data.
telsoa014fcda012018-03-09 14:13:49 +0000227struct BatchNormalizationQueueDescriptor : QueueDescriptorWithParameters<BatchNormalizationDescriptor>
228{
229 BatchNormalizationQueueDescriptor()
230 : m_Mean(nullptr)
231 , m_Variance(nullptr)
232 , m_Beta(nullptr)
233 , m_Gamma(nullptr)
234 {
235 }
236
237 const ConstCpuTensorHandle* m_Mean;
238 const ConstCpuTensorHandle* m_Variance;
239 const ConstCpuTensorHandle* m_Beta;
240 const ConstCpuTensorHandle* m_Gamma;
241
242 void Validate(const WorkloadInfo& workloadInfo) const;
243};
244
245struct ResizeBilinearQueueDescriptor : QueueDescriptorWithParameters<ResizeBilinearDescriptor>
246{
247 void Validate(const WorkloadInfo& workloadInfo) const;
248};
249
250struct FakeQuantizationQueueDescriptor : QueueDescriptorWithParameters<FakeQuantizationDescriptor>
251{
252 FakeQuantizationQueueDescriptor()
253 : m_Min(nullptr)
254 , m_Max(nullptr)
255 {
256 }
257
258 const ConstCpuTensorHandle* m_Min;
259 const ConstCpuTensorHandle* m_Max;
260
261 void Validate(const WorkloadInfo& workloadInfo) const;
262};
263
Matteo Martincighbcd3c852018-09-28 14:14:12 +0100264struct L2NormalizationQueueDescriptor : QueueDescriptorWithParameters<L2NormalizationDescriptor>
telsoa014fcda012018-03-09 14:13:49 +0000265{
266 void Validate(const WorkloadInfo& workloadInfo) const;
267};
268
269struct ConstantQueueDescriptor : QueueDescriptor
270{
271 ConstantQueueDescriptor()
272 : m_LayerOutput(nullptr)
273 {
274 }
275
276 const ConstCpuTensorHandle* m_LayerOutput;
277
278 void Validate(const WorkloadInfo& workloadInfo) const;
279};
280
281struct ReshapeQueueDescriptor : QueueDescriptorWithParameters<ReshapeDescriptor>
282{
283 void Validate(const WorkloadInfo& workloadInfo) const;
284};
285
Nattapat Chaimanowong207ef9a2018-11-02 10:57:25 +0000286struct SpaceToBatchNdQueueDescriptor : QueueDescriptorWithParameters<SpaceToBatchNdDescriptor>
287{
288 void Validate(const WorkloadInfo& workloadInfo) const;
289};
290
telsoa014fcda012018-03-09 14:13:49 +0000291struct FloorQueueDescriptor : QueueDescriptor
292{
293 void Validate(const WorkloadInfo& workloadInfo) const;
294};
295
telsoa01c577f2c2018-08-31 09:22:23 +0100296struct LstmQueueDescriptor : QueueDescriptorWithParameters<LstmDescriptor>
297{
298 LstmQueueDescriptor()
299 : m_InputToInputWeights(nullptr)
300 , m_InputToForgetWeights(nullptr)
301 , m_InputToCellWeights(nullptr)
302 , m_InputToOutputWeights(nullptr)
303 , m_RecurrentToInputWeights(nullptr)
304 , m_RecurrentToForgetWeights(nullptr)
305 , m_RecurrentToCellWeights(nullptr)
306 , m_RecurrentToOutputWeights(nullptr)
307 , m_CellToInputWeights(nullptr)
308 , m_CellToForgetWeights(nullptr)
309 , m_CellToOutputWeights(nullptr)
310 , m_InputGateBias(nullptr)
311 , m_ForgetGateBias(nullptr)
312 , m_CellBias(nullptr)
313 , m_OutputGateBias(nullptr)
314 , m_ProjectionWeights(nullptr)
315 , m_ProjectionBias(nullptr)
316 {
317 }
318
319 const ConstCpuTensorHandle* m_InputToInputWeights;
320 const ConstCpuTensorHandle* m_InputToForgetWeights;
321 const ConstCpuTensorHandle* m_InputToCellWeights;
322 const ConstCpuTensorHandle* m_InputToOutputWeights;
323 const ConstCpuTensorHandle* m_RecurrentToInputWeights;
324 const ConstCpuTensorHandle* m_RecurrentToForgetWeights;
325 const ConstCpuTensorHandle* m_RecurrentToCellWeights;
326 const ConstCpuTensorHandle* m_RecurrentToOutputWeights;
327 const ConstCpuTensorHandle* m_CellToInputWeights;
328 const ConstCpuTensorHandle* m_CellToForgetWeights;
329 const ConstCpuTensorHandle* m_CellToOutputWeights;
330 const ConstCpuTensorHandle* m_InputGateBias;
331 const ConstCpuTensorHandle* m_ForgetGateBias;
332 const ConstCpuTensorHandle* m_CellBias;
333 const ConstCpuTensorHandle* m_OutputGateBias;
334 const ConstCpuTensorHandle* m_ProjectionWeights;
335 const ConstCpuTensorHandle* m_ProjectionBias;
336
337 void Validate(const WorkloadInfo& workloadInfo) const;
338};
339
340struct ConvertFp16ToFp32QueueDescriptor : QueueDescriptor
341{
342 void Validate(const WorkloadInfo& workloadInfo) const;
343};
344
345struct ConvertFp32ToFp16QueueDescriptor : QueueDescriptor
346{
347 void Validate(const WorkloadInfo& workloadInfo) const;
348};
349
Éanna Ó Catháin4e1e1362018-11-12 11:36:34 +0000350struct BatchToSpaceNdQueueDescriptor : QueueDescriptorWithParameters<BatchToSpaceNdDescriptor>
351{
352 void Validate(const WorkloadInfo& workloadInfo) const;
353};
Conor Kennedy430b5d82018-11-14 15:28:28 +0000354
355struct StridedSliceQueueDescriptor : QueueDescriptorWithParameters<StridedSliceDescriptor>
356{
357 void Validate(const WorkloadInfo& workloadInfo) const;
358};
359
Éanna Ó Catháin20e58802018-12-04 10:29:06 +0000360// Minimum layer workload data.
kevmay0190539692018-11-29 08:40:19 +0000361struct MinimumQueueDescriptor : QueueDescriptor
362{
363 void Validate(const WorkloadInfo& workloadInfo) const;
364};
365
Matteo Martincigh59a950c2018-12-13 12:48:25 +0000366struct GreaterQueueDescriptor : QueueDescriptor
367{
368 void Validate(const WorkloadInfo& workloadInfo) const;
369};
370
Nattapat Chaimanowongac5aa1f2018-12-05 15:17:18 +0000371struct DebugQueueDescriptor : QueueDescriptorWithParameters<DebugDescriptor>
Nattapat Chaimanowonga9a1cf12018-12-03 16:06:49 +0000372{
373 void Validate(const WorkloadInfo& workloadInfo) const;
374};
375
telsoa014fcda012018-03-09 14:13:49 +0000376} //namespace armnn