Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
Kristofer Jonsson | 09273d1 | 2021-03-15 08:43:08 +0100 | [diff] [blame] | 2 | * Copyright (c) 2019-2021 Arm Limited. All rights reserved. |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 19 | /****************************************************************************** |
| 20 | * Includes |
| 21 | ******************************************************************************/ |
| 22 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 23 | #include "ethosu_driver.h" |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 24 | #include "ethosu_common.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 25 | #include "ethosu_config.h" |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 26 | #include "ethosu_device.h" |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 27 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 28 | #include <assert.h> |
Per Åstrand | 25d78c0 | 2020-04-21 14:19:44 +0200 | [diff] [blame] | 29 | #include <cmsis_compiler.h> |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 30 | #include <inttypes.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 31 | #include <stdbool.h> |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 32 | #include <stddef.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 33 | #include <stdio.h> |
| 34 | #include <stdlib.h> |
| 35 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 36 | /****************************************************************************** |
| 37 | * Defines |
| 38 | ******************************************************************************/ |
| 39 | |
| 40 | #define MACS_PER_CYCLE_LOG2_MASK 0x000F |
| 41 | #define SHRAM_SIZE_MASK 0xFF00 |
| 42 | #define SHRAM_SIZE_RIGHT_SHIFT 8 |
| 43 | #define BYTES_IN_32_BITS 4 |
| 44 | #define CUSTOM_OPTION_LENGTH_32_BIT_WORD 1 |
| 45 | #define DRIVER_ACTION_LENGTH_32_BIT_WORD 1 |
| 46 | #define OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD 2 |
| 47 | #define ETHOSU_FOURCC ('1' << 24 | 'P' << 16 | 'O' << 8 | 'C') // "Custom Operator Payload 1" |
| 48 | #define APB_START_ADDR_MASK 0x0FFF |
| 49 | #define APB_NUM_REG_BIT_SHIFT 12 |
| 50 | #define BYTES_1KB 1024 |
| 51 | #define PRODUCT_MAJOR_ETHOSU55 (4) |
| 52 | #define MASK_16_BYTE_ALIGN (0xF) |
| 53 | #define FAST_MEMORY_BASE_ADDR_INDEX 2 |
| 54 | |
| 55 | /****************************************************************************** |
| 56 | * Types |
| 57 | ******************************************************************************/ |
| 58 | |
| 59 | // Driver actions |
| 60 | enum DRIVER_ACTION_e |
| 61 | { |
| 62 | RESERVED = 0, |
| 63 | OPTIMIZER_CONFIG = 1, |
| 64 | COMMAND_STREAM = 2, |
| 65 | READ_APB_REG = 3, |
| 66 | DUMP_SHRAM = 4, |
| 67 | NOP = 5, |
| 68 | }; |
| 69 | |
| 70 | // Custom data struct |
| 71 | struct custom_data_s |
| 72 | { |
| 73 | union |
| 74 | { |
| 75 | // Driver action data |
| 76 | struct |
| 77 | { |
| 78 | // Driver action command (valid values in DRIVER_ACTION_e) |
| 79 | uint8_t driver_action_command; |
| 80 | |
| 81 | // reserved |
| 82 | uint8_t reserved; |
| 83 | |
| 84 | // Driver action data |
| 85 | union |
| 86 | { |
| 87 | // DA_CMD_OPT_CFG |
| 88 | struct |
| 89 | { |
| 90 | uint16_t rel_nbr : 4; |
| 91 | uint16_t patch_nbr : 4; |
| 92 | uint16_t opt_cfg_reserved : 8; |
| 93 | }; |
| 94 | |
| 95 | // DA_CMD_CMSTRM |
| 96 | struct |
| 97 | { |
| 98 | uint16_t length; |
| 99 | }; |
| 100 | |
| 101 | // DA_CMD_READAPB |
| 102 | struct |
| 103 | { |
| 104 | uint16_t start_address : 12; |
| 105 | uint16_t nbr_reg_minus1 : 4; |
| 106 | }; |
| 107 | |
| 108 | uint16_t driver_action_data; |
| 109 | }; |
| 110 | }; |
| 111 | |
| 112 | uint32_t word; |
| 113 | }; |
| 114 | }; |
| 115 | |
| 116 | // optimizer config struct |
| 117 | struct opt_cfg_s |
| 118 | { |
| 119 | struct custom_data_s da_data; |
| 120 | union |
| 121 | { |
| 122 | struct |
| 123 | { |
| 124 | uint32_t macs_per_cc : 4; |
| 125 | uint32_t cmd_stream_version : 4; |
| 126 | uint32_t shram_size : 8; |
| 127 | uint32_t reserved1 : 16; |
| 128 | }; |
| 129 | uint32_t npu_cfg; |
| 130 | }; |
| 131 | union |
| 132 | { |
| 133 | struct |
| 134 | { |
| 135 | uint32_t version_status : 4; |
| 136 | uint32_t version_minor : 4; |
| 137 | uint32_t version_major : 4; |
| 138 | uint32_t product_major : 4; |
| 139 | uint32_t arch_patch_rev : 4; |
| 140 | uint32_t arch_minor_rev : 8; |
| 141 | uint32_t arch_major_rev : 4; |
| 142 | }; |
| 143 | uint32_t ethosu_id; |
| 144 | }; |
| 145 | }; |
| 146 | |
| 147 | /****************************************************************************** |
| 148 | * Functions |
| 149 | ******************************************************************************/ |
| 150 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 151 | struct ethosu_driver ethosu_drv = { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 152 | .dev = {.base_address = NULL, .proto = 0, .pmccntr = {0}, .pmu_evcntr = {0, 0, 0, 0}, .pmu_evtypr = {0, 0, 0, 0}}, |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 153 | .abort_inference = false, |
| 154 | .status_error = false, |
| 155 | .dev_power_always_on = false}; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 156 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 157 | // Registered drivers linked list HEAD |
| 158 | static struct ethosu_driver *registered_drivers = NULL; |
| 159 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 160 | /* |
| 161 | * Following section handles the minimal sempahore and mutex implementation in case of baremetal applications. |
| 162 | * Weak symbols will be overwritten by RTOS definitions and implement true thread-safety. (Done in application layer) |
| 163 | */ |
| 164 | |
| 165 | // Baremetal sempahore implementation |
| 166 | struct ethosu_semaphore_t |
| 167 | { |
| 168 | int count; |
| 169 | }; |
| 170 | |
| 171 | // Minimal needed declaration to allow baremetal functionality. |
| 172 | static void *ethosu_mutex; |
| 173 | static void *ethosu_semaphore; |
| 174 | |
| 175 | void *__attribute__((weak)) ethosu_mutex_create(void) {} |
| 176 | |
| 177 | void __attribute__((weak)) ethosu_mutex_lock(void *mutex) {} |
| 178 | |
| 179 | void __attribute__((weak)) ethosu_mutex_unlock(void *mutex) {} |
| 180 | |
| 181 | // Baremetal implementation of creating a semaphore |
| 182 | void *__attribute__((weak)) ethosu_semaphore_create(void) |
| 183 | { |
| 184 | struct ethosu_semaphore_t *sem = malloc(sizeof(*sem)); |
| 185 | sem->count = 1; |
| 186 | return sem; |
| 187 | } |
| 188 | |
| 189 | // Baremetal simulation of waiting/sleeping for and then taking a semaphore using intrisics |
| 190 | void __attribute__((weak)) ethosu_semaphore_take(void *sem) |
| 191 | { |
| 192 | struct ethosu_semaphore_t *s = sem; |
| 193 | while (s->count <= 0) |
| 194 | { |
| 195 | __WFE(); |
| 196 | } |
| 197 | s->count--; |
| 198 | } |
| 199 | |
| 200 | // Baremetal simulation of giving a semaphore and waking up processes using intrinsics |
| 201 | void __attribute__((weak)) ethosu_semaphore_give(void *sem) |
| 202 | { |
| 203 | struct ethosu_semaphore_t *s = sem; |
| 204 | s->count++; |
| 205 | __SEV(); |
| 206 | } |
| 207 | // <--- End of semaphore and mutex implementations |
| 208 | |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 209 | static int ethosu_soft_reset_and_restore(struct ethosu_driver *drv); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 210 | |
Kristofer Jonsson | 09273d1 | 2021-03-15 08:43:08 +0100 | [diff] [blame] | 211 | void __attribute__((weak)) ethosu_irq_handler_v2(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 212 | { |
| 213 | uint8_t irq_raised = 0; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 214 | |
| 215 | LOG_DEBUG("Interrupt. status=0x%08x, qread=%d\n", |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 216 | ethosu_read_reg(&drv->dev, NPU_REG_STATUS), |
| 217 | ethosu_read_reg(&drv->dev, NPU_REG_QREAD)); |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 218 | |
| 219 | // Verify that interrupt has been raised |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 220 | (void)ethosu_is_irq_raised(&drv->dev, &irq_raised); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 221 | ASSERT(irq_raised == 1); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 222 | drv->irq_triggered = true; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 223 | |
| 224 | // Clear interrupt |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 225 | (void)ethosu_clear_irq_status(&drv->dev); |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 226 | |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 227 | // Verify that interrupt has been successfully cleared |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 228 | (void)ethosu_is_irq_raised(&drv->dev, &irq_raised); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 229 | ASSERT(irq_raised == 0); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 230 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 231 | if (ethosu_status_has_error(&drv->dev)) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 232 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 233 | ethosu_soft_reset_and_restore(drv); |
| 234 | drv->status_error = true; |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 235 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 236 | |
| 237 | ethosu_semaphore_give(drv->semaphore); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 238 | } |
| 239 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 240 | static inline void wait_for_irq(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 241 | { |
| 242 | while (1) |
| 243 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 244 | if (drv->irq_triggered || drv->abort_inference) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 245 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 246 | drv->irq_triggered = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 247 | break; |
| 248 | } |
| 249 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 250 | ethosu_semaphore_take(drv->semaphore); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 251 | } |
| 252 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 253 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 254 | static int handle_optimizer_config(struct ethosu_driver *drv, struct opt_cfg_s *opt_cfg_p); |
| 255 | static int handle_command_stream(struct ethosu_driver *drv, |
| 256 | const uint8_t *cmd_stream, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 257 | const int cms_length, |
| 258 | const uint64_t *base_addr, |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 259 | const size_t *base_addr_size, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 260 | const int num_base_addr); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 261 | static int read_apb_reg(struct ethosu_driver *drv, uint16_t); |
| 262 | static int dump_shram(struct ethosu_driver *drv); |
| 263 | static void dump_npu_register(struct ethosu_driver *drv, int npu_reg, int npu_reg_end); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 264 | static void dump_command_stream(const uint32_t *cmd_stream, const int cms_length, int qread); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 265 | static void npu_axi_init(struct ethosu_driver *drv); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 266 | static struct ethosu_driver *ethosu_find_and_reserve_driver(void); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 267 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 268 | int ethosu_init_v4(struct ethosu_driver *drv, |
| 269 | const void *base_address, |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 270 | const void *fast_memory, |
| 271 | const size_t fast_memory_size, |
| 272 | uint32_t secure_enable, |
| 273 | uint32_t privilege_enable) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 274 | { |
| 275 | int return_code = 0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 276 | |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 277 | LOG_INFO("%s. base_address=%p, fast_memory=%p, fast_memory_size=%zu, secure=%" PRIu32 ", privileged=%" PRIu32 "\n", |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 278 | __FUNCTION__, |
| 279 | base_address, |
| 280 | fast_memory, |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 281 | fast_memory_size, |
| 282 | secure_enable, |
| 283 | privilege_enable); |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 284 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 285 | if (!ethosu_mutex) |
| 286 | { |
| 287 | ethosu_mutex = ethosu_mutex_create(); |
| 288 | } |
| 289 | |
| 290 | if (!ethosu_semaphore) |
| 291 | { |
| 292 | ethosu_semaphore = ethosu_semaphore_create(); |
| 293 | } |
| 294 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 295 | ethosu_register_driver(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 296 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 297 | drv->fast_memory = (uint32_t)fast_memory; |
| 298 | drv->fast_memory_size = fast_memory_size; |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 299 | drv->irq_triggered = false; |
| 300 | drv->semaphore = ethosu_semaphore_create(); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 301 | |
| 302 | if (ETHOSU_SUCCESS != ethosu_dev_init(&drv->dev, base_address, secure_enable, privilege_enable)) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 303 | { |
| 304 | LOG_ERR("Failed in ethosu_dev_init"); |
| 305 | return -1; |
| 306 | } |
| 307 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 308 | if (ETHOSU_SUCCESS != ethosu_set_clock_and_power(&drv->dev, ETHOSU_CLOCK_Q_DISABLE, ETHOSU_POWER_Q_DISABLE)) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 309 | { |
| 310 | LOG_ERR("Failed to disable clock-q & power-q for Ethos-U\n"); |
| 311 | return -1; |
| 312 | } |
| 313 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 314 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 315 | { |
| 316 | return -1; |
| 317 | } |
Kristofer Jonsson | daa0d20 | 2020-05-12 12:23:16 +0200 | [diff] [blame] | 318 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 319 | if (ETHOSU_SUCCESS != ethosu_wait_for_reset(&drv->dev)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 320 | { |
| 321 | LOG_ERR("Failed reset of Ethos-U\n"); |
| 322 | return -1; |
| 323 | } |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 324 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 325 | drv->status_error = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 326 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 327 | return return_code; |
| 328 | } |
| 329 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 330 | int ethosu_get_version_v2(struct ethosu_driver *drv, struct ethosu_version *version) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 331 | { |
| 332 | int return_code = 0; |
| 333 | |
| 334 | if (NULL != version) |
| 335 | { |
| 336 | struct ethosu_id id; |
| 337 | struct ethosu_config cfg; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 338 | (void)ethosu_get_id(&drv->dev, &id); |
| 339 | (void)ethosu_get_config(&drv->dev, &cfg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 340 | |
| 341 | version->id.version_status = id.version_status; |
| 342 | version->id.version_minor = id.version_minor; |
| 343 | version->id.version_major = id.version_major; |
| 344 | version->id.product_major = id.product_major; |
| 345 | version->id.arch_patch_rev = id.arch_patch_rev; |
| 346 | version->id.arch_minor_rev = id.arch_minor_rev; |
| 347 | version->id.arch_major_rev = id.arch_major_rev; |
| 348 | version->id.driver_patch_rev = ETHOSU_DRIVER_VERSION_PATCH; |
| 349 | version->id.driver_minor_rev = ETHOSU_DRIVER_VERSION_MINOR; |
| 350 | version->id.driver_major_rev = ETHOSU_DRIVER_VERSION_MAJOR; |
| 351 | version->cfg.macs_per_cc = cfg.macs_per_cc; |
| 352 | version->cfg.cmd_stream_version = cfg.cmd_stream_version; |
| 353 | version->cfg.shram_size = cfg.shram_size; |
| 354 | } |
| 355 | else |
| 356 | { |
| 357 | return_code = -1; |
| 358 | } |
| 359 | |
| 360 | return return_code; |
| 361 | } |
| 362 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 363 | int ethosu_invoke_v3(struct ethosu_driver *drv, |
| 364 | const void *custom_data_ptr, |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 365 | const int custom_data_size, |
| 366 | const uint64_t *base_addr, |
| 367 | const size_t *base_addr_size, |
| 368 | const int num_base_addr) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 369 | { |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 370 | const struct custom_data_s *data_ptr = custom_data_ptr; |
| 371 | const struct custom_data_s *data_end = custom_data_ptr + custom_data_size; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 372 | int return_code = 0; |
| 373 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 374 | LOG_INFO("%s\n", __FUNCTION__); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 375 | |
| 376 | // First word in custom_data_ptr should contain "Custom Operator Payload 1" |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 377 | if (data_ptr->word != ETHOSU_FOURCC) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 378 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 379 | LOG_ERR("Custom Operator Payload: %" PRIu32 " is not correct, expected %x\n", data_ptr->word, ETHOSU_FOURCC); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 380 | return -1; |
| 381 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 382 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 383 | // Custom data length must be a multiple of 32 bits |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 384 | if ((custom_data_size % BYTES_IN_32_BITS) != 0) |
| 385 | { |
| 386 | LOG_ERR("ethosu_invoke ERROR custom_data_size=0x%x not a multiple of 4\n", custom_data_size); |
| 387 | return -1; |
| 388 | } |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 389 | |
| 390 | ++data_ptr; |
| 391 | |
| 392 | // Adjust base address to fast memory area |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 393 | if (drv->fast_memory != 0 && num_base_addr >= FAST_MEMORY_BASE_ADDR_INDEX) |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 394 | { |
| 395 | uint64_t *fast_memory = (uint64_t *)&base_addr[FAST_MEMORY_BASE_ADDR_INDEX]; |
| 396 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 397 | if (base_addr_size != NULL && base_addr_size[FAST_MEMORY_BASE_ADDR_INDEX] > drv->fast_memory_size) |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 398 | { |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 399 | LOG_ERR("Fast memory area too small. fast_memory_size=%u, base_addr_size=%u\n", |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 400 | drv->fast_memory_size, |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 401 | base_addr_size[FAST_MEMORY_BASE_ADDR_INDEX]); |
| 402 | return -1; |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 403 | } |
Kristofer Jonsson | 4c94b30 | 2020-11-06 10:33:21 +0100 | [diff] [blame] | 404 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 405 | *fast_memory = drv->fast_memory; |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 406 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 407 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 408 | if (!drv->dev_power_always_on) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 409 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 410 | // Only soft reset if securty state or privilege level needs changing |
| 411 | if (drv->dev.proto != ethosu_read_reg(&drv->dev, NPU_REG_PROT)) |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 412 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 413 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 414 | { |
| 415 | return -1; |
| 416 | } |
Per Åstrand | 849cf69 | 2020-11-24 07:39:55 +0100 | [diff] [blame] | 417 | } |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 418 | |
| 419 | drv->status_error = false; |
| 420 | ethosu_set_clock_and_power(&drv->dev, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_DISABLE); |
| 421 | ethosu_restore_pmu_config(&drv->dev); |
| 422 | npu_axi_init(drv); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 423 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 424 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 425 | drv->status_error = false; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 426 | |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 427 | while (data_ptr < data_end) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 428 | { |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 429 | int ret = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 430 | switch (data_ptr->driver_action_command) |
| 431 | { |
| 432 | case OPTIMIZER_CONFIG: |
| 433 | LOG_INFO("ethosu_invoke OPTIMIZER_CONFIG\n"); |
| 434 | struct opt_cfg_s *opt_cfg_p = (struct opt_cfg_s *)data_ptr; |
| 435 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 436 | ret = handle_optimizer_config(drv, opt_cfg_p); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 437 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD; |
| 438 | break; |
| 439 | case COMMAND_STREAM: |
| 440 | LOG_INFO("ethosu_invoke COMMAND_STREAM\n"); |
| 441 | void *command_stream = (uint8_t *)(data_ptr) + sizeof(struct custom_data_s); |
| 442 | int cms_length = (data_ptr->reserved << 16) | data_ptr->length; |
| 443 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 444 | drv->abort_inference = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 445 | // It is safe to clear this flag without atomic, because npu is not running. |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 446 | drv->irq_triggered = false; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 447 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 448 | ret = handle_command_stream(drv, command_stream, cms_length, base_addr, base_addr_size, num_base_addr); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 449 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 450 | if (return_code == -1 && drv->abort_inference) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 451 | { |
| 452 | uint32_t qread = 0; |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 453 | ethosu_get_qread(&drv->dev, &qread); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 454 | LOG_ERR("NPU timeout\n"); |
| 455 | dump_command_stream(command_stream, cms_length, qread); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 456 | dump_npu_register(drv, 0x200, 0x2BF); |
| 457 | dump_npu_register(drv, 0x800, 0xB3F); |
| 458 | dump_shram(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 459 | } |
| 460 | |
| 461 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + cms_length; |
| 462 | break; |
| 463 | case READ_APB_REG: |
| 464 | LOG_INFO("ethosu_invoke READ_APB_REG\n"); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 465 | ret = read_apb_reg(drv, data_ptr->driver_action_data); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 466 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 467 | break; |
| 468 | case DUMP_SHRAM: |
| 469 | LOG_INFO("ethosu_invoke DUMP_SHRAM\n"); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 470 | ret = dump_shram(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 471 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 472 | break; |
| 473 | case NOP: |
| 474 | LOG_INFO("ethosu_invoke NOP\n"); |
| 475 | data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; |
| 476 | break; |
| 477 | default: |
| 478 | LOG_ERR("ethosu_invoke UNSUPPORTED driver_action_command %d \n", data_ptr->driver_action_command); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 479 | ret = -1; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 480 | break; |
| 481 | } |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 482 | if (ret != 0) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 483 | { |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 484 | return_code = -1; |
| 485 | break; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 486 | } |
| 487 | } |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 488 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 489 | if (!drv->status_error && !drv->dev_power_always_on) |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 490 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 491 | ethosu_save_pmu_counters(&drv->dev); |
| 492 | ethosu_set_clock_and_power(&drv->dev, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_ENABLE); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 493 | } |
Kristofer Jonsson | 2b201c3 | 2020-09-02 16:42:43 +0200 | [diff] [blame] | 494 | |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 495 | return return_code; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 496 | } |
| 497 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 498 | void ethosu_abort_v2(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 499 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 500 | drv->abort_inference = true; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 501 | } |
| 502 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 503 | void ethosu_set_power_mode_v2(struct ethosu_driver *drv, bool always_on) |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 504 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 505 | drv->dev_power_always_on = always_on; |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 506 | |
| 507 | if (always_on) |
| 508 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 509 | npu_axi_init(drv); |
| 510 | } |
| 511 | } |
| 512 | |
| 513 | int ethosu_register_driver(struct ethosu_driver *drv) |
| 514 | { |
| 515 | // Safeguard check for if driver is already registered |
| 516 | struct ethosu_driver *cur = registered_drivers; |
| 517 | while (cur != NULL) |
| 518 | { |
| 519 | if (cur == drv) |
| 520 | { |
| 521 | LOG_ERR("%s: NPU driver at address %p is already registered.\n", __FUNCTION__, drv); |
| 522 | return -1; |
| 523 | } |
| 524 | cur = cur->next; |
| 525 | } |
| 526 | |
| 527 | drv->next = registered_drivers; |
| 528 | // Designate new registered driver HEAD |
| 529 | registered_drivers = drv; |
| 530 | |
| 531 | LOG_INFO("%s: New NPU driver at address %p is registered.\n", __FUNCTION__, drv); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 532 | return 0; |
| 533 | } |
| 534 | |
| 535 | int ethosu_deregister_driver(struct ethosu_driver *drv) |
| 536 | { |
| 537 | struct ethosu_driver *cur = registered_drivers; |
| 538 | struct ethosu_driver **prev = ®istered_drivers; |
| 539 | |
| 540 | while (cur != NULL) |
| 541 | { |
| 542 | if (cur == drv) |
| 543 | { |
| 544 | *prev = cur->next; |
| 545 | LOG_INFO("%s: NPU driver at address %p is deregistered.\n", __FUNCTION__, drv); |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | prev = &cur->next; |
| 550 | cur = cur->next; |
| 551 | } |
| 552 | |
| 553 | LOG_ERR("%s: NPU driver at address %p does not match a registered driver and therefore may not be deregistered.\n", |
| 554 | __FUNCTION__, |
| 555 | drv); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 556 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 557 | return -1; |
| 558 | } |
| 559 | |
| 560 | struct ethosu_driver *ethosu_reserve_driver(void) |
| 561 | { |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 562 | struct ethosu_driver *drv = NULL; |
| 563 | |
| 564 | do |
| 565 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 566 | ethosu_mutex_lock(ethosu_mutex); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 567 | drv = ethosu_find_and_reserve_driver(); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 568 | ethosu_mutex_unlock(ethosu_mutex); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 569 | |
| 570 | if (drv != NULL) |
| 571 | { |
| 572 | break; |
| 573 | } |
| 574 | |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 575 | LOG_INFO("%s - Waiting for driver \n", __FUNCTION__); |
| 576 | ethosu_semaphore_take(ethosu_semaphore); |
Anton Moberg | df386e0 | 2021-02-02 11:26:48 +0100 | [diff] [blame] | 577 | |
| 578 | } while (1); |
| 579 | |
| 580 | return drv; |
| 581 | } |
| 582 | |
| 583 | static struct ethosu_driver *ethosu_find_and_reserve_driver(void) |
| 584 | { |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 585 | struct ethosu_driver *drv = registered_drivers; |
| 586 | |
| 587 | while (drv != NULL) |
| 588 | { |
| 589 | if (!drv->reserved) |
| 590 | { |
| 591 | drv->reserved = true; |
| 592 | LOG_INFO("%s - Driver %p reserved.\n", __FUNCTION__, drv); |
| 593 | return drv; |
| 594 | } |
| 595 | drv = drv->next; |
| 596 | } |
| 597 | |
| 598 | LOG_INFO("%s: No available drivers.\n", __FUNCTION__, drv); |
| 599 | |
| 600 | return NULL; |
| 601 | } |
| 602 | |
| 603 | void ethosu_release_driver(struct ethosu_driver *drv) |
| 604 | { |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 605 | ethosu_mutex_lock(ethosu_mutex); |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 606 | if (drv != NULL && drv->reserved) |
| 607 | { |
| 608 | drv->reserved = false; |
| 609 | LOG_INFO("%s - Driver %p released\n", __FUNCTION__, drv); |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 610 | ethosu_semaphore_give(ethosu_semaphore); |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 611 | } |
Anton Moberg | dfed5fd | 2021-03-11 14:41:11 +0100 | [diff] [blame^] | 612 | ethosu_mutex_unlock(ethosu_mutex); |
Anton Moberg | 8d65b6f | 2020-12-21 09:37:18 +0100 | [diff] [blame] | 613 | } |
| 614 | |
| 615 | static int ethosu_soft_reset_and_restore(struct ethosu_driver *drv) |
| 616 | { |
| 617 | |
| 618 | if (ETHOSU_SUCCESS != ethosu_soft_reset(&drv->dev)) |
| 619 | { |
| 620 | return -1; |
| 621 | } |
| 622 | |
| 623 | ethosu_set_clock_and_power(&drv->dev, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_DISABLE); |
| 624 | |
| 625 | npu_axi_init(drv); |
| 626 | ethosu_restore_pmu_config(&drv->dev); |
| 627 | |
| 628 | return 0; |
| 629 | } |
| 630 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 631 | static int handle_optimizer_config(struct ethosu_driver *drv, struct opt_cfg_s *opt_cfg_p) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 632 | { |
| 633 | struct ethosu_config cfg; |
| 634 | struct ethosu_id id; |
| 635 | int return_code = 0; |
| 636 | |
| 637 | LOG_INFO("handle_optimizer_config:\n"); |
| 638 | LOG_INFO("Optimizer release nbr: %d patch: %d\n", opt_cfg_p->da_data.rel_nbr, opt_cfg_p->da_data.patch_nbr); |
| 639 | LOG_INFO("Optimizer config cmd_stream_version: %d macs_per_cc: %d shram_size: %d\n", |
| 640 | opt_cfg_p->cmd_stream_version, |
| 641 | opt_cfg_p->macs_per_cc, |
| 642 | opt_cfg_p->shram_size); |
| 643 | LOG_INFO("Optimizer config Ethos-U version: %d.%d.%d\n", |
| 644 | opt_cfg_p->arch_major_rev, |
| 645 | opt_cfg_p->arch_minor_rev, |
| 646 | opt_cfg_p->arch_patch_rev); |
| 647 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 648 | (void)ethosu_get_config(&drv->dev, &cfg); |
| 649 | (void)ethosu_get_id(&drv->dev, &id); |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 650 | LOG_INFO("Ethos-U config cmd_stream_version: %" PRIu32 " macs_per_cc: %" PRIu32 " shram_size: %" PRIu32 "\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 651 | cfg.cmd_stream_version, |
| 652 | cfg.macs_per_cc, |
| 653 | cfg.shram_size); |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 654 | LOG_INFO("Ethos-U version: %" PRIu32 ".%" PRIu32 ".%" PRIu32 "\n", |
| 655 | id.arch_major_rev, |
| 656 | id.arch_minor_rev, |
| 657 | id.arch_patch_rev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 658 | |
| 659 | if ((cfg.macs_per_cc != opt_cfg_p->macs_per_cc) || (cfg.shram_size != opt_cfg_p->shram_size) || |
| 660 | (cfg.cmd_stream_version != opt_cfg_p->cmd_stream_version)) |
| 661 | { |
| 662 | if (cfg.macs_per_cc != opt_cfg_p->macs_per_cc) |
| 663 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 664 | LOG_ERR("NPU config mismatch: npu.macs_per_cc=%" PRIu32 " optimizer.macs_per_cc=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 665 | cfg.macs_per_cc, |
| 666 | opt_cfg_p->macs_per_cc); |
| 667 | } |
| 668 | if (cfg.shram_size != opt_cfg_p->shram_size) |
| 669 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 670 | LOG_ERR("NPU config mismatch: npu.shram_size=%" PRIu32 " optimizer.shram_size=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 671 | cfg.shram_size, |
| 672 | opt_cfg_p->shram_size); |
| 673 | } |
| 674 | if (cfg.cmd_stream_version != opt_cfg_p->cmd_stream_version) |
| 675 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 676 | LOG_ERR("NPU config mismatch: npu.cmd_stream_version=%" PRIu32 " optimizer.cmd_stream_version=%d\n", |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 677 | cfg.cmd_stream_version, |
| 678 | opt_cfg_p->cmd_stream_version); |
| 679 | } |
| 680 | return_code = -1; |
| 681 | } |
| 682 | |
Douglas Troha | 91e0be5 | 2021-01-18 13:57:38 +0100 | [diff] [blame] | 683 | if ((id.arch_major_rev != opt_cfg_p->arch_major_rev) || (id.arch_minor_rev < opt_cfg_p->arch_minor_rev)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 684 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 685 | LOG_ERR("NPU arch mismatch: npu.arch=%" PRIu32 ".%" PRIu32 ".%" PRIu32 " optimizer.arch=%d.%d.%d\n", |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 686 | id.arch_major_rev, |
| 687 | id.arch_minor_rev, |
| 688 | id.arch_patch_rev, |
| 689 | opt_cfg_p->arch_major_rev, |
| 690 | opt_cfg_p->arch_minor_rev, |
| 691 | opt_cfg_p->arch_patch_rev); |
| 692 | return_code = -1; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 693 | } |
| 694 | |
| 695 | #if !defined(LOG_ENABLED) |
| 696 | UNUSED(opt_cfg_p); |
| 697 | #endif |
| 698 | return return_code; |
| 699 | } |
| 700 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 701 | static void npu_axi_init(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 702 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 703 | ethosu_set_qconfig(&drv->dev, NPU_QCONFIG); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 704 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 705 | ethosu_set_regioncfg(&drv->dev, 0, NPU_REGIONCFG_0); |
| 706 | ethosu_set_regioncfg(&drv->dev, 1, NPU_REGIONCFG_1); |
| 707 | ethosu_set_regioncfg(&drv->dev, 2, NPU_REGIONCFG_2); |
| 708 | ethosu_set_regioncfg(&drv->dev, 3, NPU_REGIONCFG_3); |
| 709 | ethosu_set_regioncfg(&drv->dev, 4, NPU_REGIONCFG_4); |
| 710 | ethosu_set_regioncfg(&drv->dev, 5, NPU_REGIONCFG_5); |
| 711 | ethosu_set_regioncfg(&drv->dev, 6, NPU_REGIONCFG_6); |
| 712 | ethosu_set_regioncfg(&drv->dev, 7, NPU_REGIONCFG_7); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 713 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 714 | (void)ethosu_set_axi_limit0(&drv->dev, |
| 715 | AXI_LIMIT0_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 716 | AXI_LIMIT0_MEM_TYPE, |
| 717 | AXI_LIMIT0_MAX_OUTSTANDING_READS, |
| 718 | AXI_LIMIT0_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 719 | (void)ethosu_set_axi_limit1(&drv->dev, |
| 720 | AXI_LIMIT1_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 721 | AXI_LIMIT1_MEM_TYPE, |
| 722 | AXI_LIMIT1_MAX_OUTSTANDING_READS, |
| 723 | AXI_LIMIT1_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 724 | (void)ethosu_set_axi_limit2(&drv->dev, |
| 725 | AXI_LIMIT2_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 726 | AXI_LIMIT2_MEM_TYPE, |
| 727 | AXI_LIMIT2_MAX_OUTSTANDING_READS, |
| 728 | AXI_LIMIT2_MAX_OUTSTANDING_WRITES); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 729 | (void)ethosu_set_axi_limit3(&drv->dev, |
| 730 | AXI_LIMIT3_MAX_BEATS_BYTES, |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 731 | AXI_LIMIT3_MEM_TYPE, |
| 732 | AXI_LIMIT3_MAX_OUTSTANDING_READS, |
| 733 | AXI_LIMIT3_MAX_OUTSTANDING_WRITES); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 734 | } |
| 735 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 736 | /* Default implementation to flush the data cache. Override if available on the targeted device. |
| 737 | * Passing NULL as p argument expects the whole cache to be flushed. |
| 738 | */ |
| 739 | void __attribute__((weak)) ethosu_flush_dcache(uint32_t *p, size_t bytes) |
| 740 | { |
| 741 | (void)p; |
| 742 | (void)bytes; |
| 743 | } |
| 744 | |
| 745 | /* Default implementation to invalidate the data cache. Override if available on the targeted device. |
| 746 | * Passing NULL as p argument expects the whole cache to be flushed. |
| 747 | */ |
| 748 | void __attribute__((weak)) ethosu_invalidate_dcache(uint32_t *p, size_t bytes) |
| 749 | { |
| 750 | (void)p; |
| 751 | (void)bytes; |
| 752 | } |
| 753 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 754 | static int handle_command_stream(struct ethosu_driver *drv, |
| 755 | const uint8_t *cmd_stream, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 756 | const int cms_length, |
| 757 | const uint64_t *base_addr, |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 758 | const size_t *base_addr_size, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 759 | const int num_base_addr) |
| 760 | { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 761 | uint32_t qread = 0; |
| 762 | uint32_t cms_bytes = cms_length * BYTES_IN_32_BITS; |
| 763 | ptrdiff_t cmd_stream_ptr = (ptrdiff_t)cmd_stream; |
| 764 | |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 765 | LOG_INFO("handle_command_stream: cmd_stream=%p, cms_length %d\n", cmd_stream, cms_length); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 766 | |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 767 | if (0 != ((ptrdiff_t)cmd_stream & MASK_16_BYTE_ALIGN)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 768 | { |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 769 | LOG_ERR("Error: Command stream addr %p not aligned to 16 bytes\n", cmd_stream); |
| 770 | return -1; |
| 771 | } |
| 772 | |
| 773 | bool base_addr_invalid = false; |
| 774 | for (int i = 0; i < num_base_addr; i++) |
| 775 | { |
| 776 | if (0 != (base_addr[i] & MASK_16_BYTE_ALIGN)) |
| 777 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 778 | LOG_ERR("Error: Base addr %d: 0x%llx not aligned to 16 bytes\n", i, base_addr[i]); |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 779 | base_addr_invalid = true; |
| 780 | } |
| 781 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 782 | |
Bhavik Patel | bf7ae63 | 2020-06-11 21:00:16 +0200 | [diff] [blame] | 783 | if (base_addr_invalid) |
| 784 | { |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 785 | return -1; |
| 786 | } |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 787 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 788 | /* Flush the cache if available on our CPU. |
| 789 | * The upcasting to uin32_t* is ok since the pointer never is dereferenced. |
| 790 | * The base_addr_size is null if invoking from prior to invoke_V2, in that case |
| 791 | * the whole cache is being flushed. |
| 792 | */ |
| 793 | |
| 794 | if (base_addr_size != NULL) |
| 795 | { |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 796 | ethosu_flush_dcache((uint32_t *)cmd_stream_ptr, cms_bytes); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 797 | for (int i = 0; i < num_base_addr; i++) |
| 798 | { |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 799 | ethosu_flush_dcache((uint32_t *)(uintptr_t)base_addr[i], base_addr_size[i]); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 800 | } |
| 801 | } |
| 802 | else |
| 803 | { |
| 804 | ethosu_flush_dcache(NULL, 0); |
| 805 | } |
| 806 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 807 | if (ETHOSU_SUCCESS != ethosu_run_command_stream(&drv->dev, cmd_stream, cms_bytes, base_addr, num_base_addr)) |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 808 | { |
| 809 | return -1; |
| 810 | } |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 811 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 812 | wait_for_irq(drv); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 813 | |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 814 | if (drv->status_error) |
| 815 | { |
| 816 | return -1; |
| 817 | } |
| 818 | |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 819 | if (base_addr_size != NULL) |
| 820 | { |
| 821 | for (int i = 0; i < num_base_addr; i++) |
| 822 | { |
Bhavik Patel | 033bb1b | 2020-12-17 15:33:33 +0100 | [diff] [blame] | 823 | ethosu_invalidate_dcache((uint32_t *)(uintptr_t)base_addr[i], base_addr_size[i]); |
Per Åstrand | 3c8afcc | 2020-10-20 10:29:59 +0200 | [diff] [blame] | 824 | } |
| 825 | } |
| 826 | else |
| 827 | { |
| 828 | ethosu_invalidate_dcache(NULL, 0); |
| 829 | } |
| 830 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 831 | (void)ethosu_get_qread(&drv->dev, &qread); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 832 | if (qread != cms_bytes) |
| 833 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 834 | LOG_WARN( |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 835 | "Failure: IRQ received but qread (%" PRIu32 ") not at end of stream (%" PRIu32 ").\n", qread, cms_bytes); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 836 | return -1; |
| 837 | } |
| 838 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 839 | return 0; |
| 840 | } |
| 841 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 842 | static int read_apb_reg(struct ethosu_driver *drv, uint16_t da_data) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 843 | { |
| 844 | uint32_t *reg_p; |
| 845 | uint32_t start_address = (uint32_t)(da_data & APB_START_ADDR_MASK); |
| 846 | uint16_t num_reg = (da_data >> APB_NUM_REG_BIT_SHIFT) + 1; |
| 847 | |
| 848 | reg_p = (uint32_t *)malloc(num_reg * sizeof(uint32_t)); |
| 849 | if (reg_p == NULL) |
| 850 | { |
| 851 | LOG_INFO("read_apb_reg, Error! memory not allocated."); |
| 852 | return -1; |
| 853 | } |
| 854 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 855 | if (ETHOSU_SUCCESS == ethosu_read_apb_reg(&drv->dev, start_address, num_reg, reg_p)) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 856 | { |
| 857 | for (int i = 0; i < num_reg; i++) |
| 858 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 859 | LOG_INFO( |
| 860 | "NPU_REG ADDR 0x%04" PRIu32 " = 0x%08" PRIu32 "\n", (start_address + (i * BYTES_IN_32_BITS)), reg_p[i]); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 861 | } |
| 862 | } |
| 863 | else |
| 864 | { |
| 865 | free(reg_p); |
| 866 | return -1; |
| 867 | } |
| 868 | |
| 869 | free(reg_p); |
| 870 | return 0; |
| 871 | } |
| 872 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 873 | static int dump_shram(struct ethosu_driver *drv) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 874 | { |
| 875 | struct ethosu_config cfg; |
| 876 | uint32_t *shram_p; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 877 | (void)ethosu_get_config(&drv->dev, &cfg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 878 | |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 879 | LOG_INFO("dump_shram size = %" PRIu32 " KB\n", cfg.shram_size); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 880 | |
| 881 | shram_p = (uint32_t *)malloc(BYTES_1KB); |
| 882 | if (shram_p == NULL) |
| 883 | { |
| 884 | LOG_ERR("read_shram, Error! memory not allocated."); |
| 885 | return -1; |
| 886 | } |
| 887 | |
| 888 | for (uint32_t i = 0; i < cfg.shram_size; i++) |
| 889 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 890 | ethosu_get_shram_data(&drv->dev, i, (uint32_t *)shram_p); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 891 | // Output 1KB of SHRAM |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 892 | LOG_INFO("***SHRAM SECTION %" PRIu32 "***\n", i); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 893 | for (int j = 0; j < (BYTES_1KB / BYTES_IN_32_BITS); j++) |
| 894 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 895 | LOG_INFO("[0x%04" PRIx32 "] %" PRIx32 "\n", (i * 1024 + j * 4), shram_p[j]); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 896 | } |
| 897 | } |
| 898 | free(shram_p); |
| 899 | |
| 900 | return 0; |
| 901 | } |
| 902 | |
| 903 | typedef struct |
| 904 | { |
| 905 | int number; |
| 906 | const char *name; |
| 907 | } name_lookup_t; |
| 908 | |
| 909 | static const name_lookup_t npu_reg_name_tbl[] = { |
| 910 | {0x200, "KERNEL_X"}, |
| 911 | {0x204, "KERNEL_Y"}, |
| 912 | {0x208, "KERNEL_W_M1"}, |
| 913 | {0x20C, "KERNEL_H_M1"}, |
| 914 | {0x210, "OFM_CBLK_WIDTH_M1"}, |
| 915 | {0x214, "OFM_CBLK_HEIGHT_M1"}, |
| 916 | {0x218, "OFM_CBLK_DEPTH_M1"}, |
| 917 | {0x21c, "IFM_CBLK_DEPTH_M1"}, |
| 918 | {0x220, "OFM_X"}, |
| 919 | {0x224, "OFM_Y"}, |
| 920 | {0x228, "OFM_Z"}, |
| 921 | {0x22C, "IFM_Z"}, |
| 922 | {0x230, "PAD_TOP"}, |
| 923 | {0x234, "PAD_LEFT"}, |
| 924 | {0x238, "IFM_CBLK_WIDTH"}, |
| 925 | {0x23C, "IFM_CBLK_HEIGHT"}, |
| 926 | {0x240, "DMA_IFM_SRC"}, |
| 927 | {0x244, "DMA_IFM_SRC_HI"}, |
| 928 | {0x248, "DMA_IFM_DST"}, |
| 929 | {0x24c, "DMA_OFM_SRC"}, |
| 930 | {0x250, "DMA_OFM_DST"}, |
| 931 | {0x254, "DMA_OFM_DST_HI"}, |
| 932 | {0x258, "DMA_WEIGHT_SRC"}, |
| 933 | {0x25c, "DMA_WEIGHT_SRC_HI"}, |
| 934 | {0x260, "DMA_CMD_SRC"}, |
| 935 | {0x264, "DMA_CMD_SRC_HI"}, |
| 936 | {0x268, "DMA_CMD_SIZE"}, |
| 937 | {0x26c, "DMA_M2M_SRC"}, |
| 938 | {0x270, "DMA_M2M_SRC_HI"}, |
| 939 | {0x274, "DMA_M2M_DST"}, |
| 940 | {0x278, "DMA_M2M_DST_HI"}, |
| 941 | {0x27c, "CURRENT_QREAD"}, |
| 942 | {0x280, "DMA_SCALE_SRC"}, |
| 943 | {0x284, "DMA_SCALE_SRC_HI"}, |
| 944 | {0x2BC, "CURRENT_CMD"}, |
| 945 | {0x800, "IFM_PAD_TOP"}, |
| 946 | {0x804, "IFM_PAD_LEFT"}, |
| 947 | {0x808, "IFM_PAD_RIGHT"}, |
| 948 | {0x80C, "IFM_PAD_BOTTOM"}, |
| 949 | {0x810, "IFM_DEPTH_M1"}, |
| 950 | {0x814, "IFM_PRECISION"}, |
| 951 | {0x81C, "IFM_UPSCALE"}, |
| 952 | {0x824, "IFM_ZERO_POINT"}, |
| 953 | {0x828, "IFM_WIDTH0_M1"}, |
| 954 | {0x82C, "IFM_HEIGHT0_M1"}, |
| 955 | {0x830, "IFM_HEIGHT1_M1"}, |
| 956 | {0x834, "IFM_IB_END"}, |
| 957 | {0x83C, "IFM_REGION"}, |
| 958 | {0x844, "OFM_WIDTH_M1"}, |
| 959 | {0x848, "OFM_HEIGHT_M1"}, |
| 960 | {0x84C, "OFM_DEPTH_M1"}, |
| 961 | {0x850, "OFM_PRECISION"}, |
| 962 | {0x854, "OFM_BLK_WIDTH_M1"}, |
| 963 | {0x858, "OFM_BLK_HEIGHT_M1"}, |
| 964 | {0x85C, "OFM_BLK_DEPTH_M1"}, |
| 965 | {0x860, "OFM_ZERO_POINT"}, |
| 966 | {0x868, "OFM_WIDTH0_M1"}, |
| 967 | {0x86C, "OFM_HEIGHT0_M1"}, |
| 968 | {0x870, "OFM_HEIGHT1_M1"}, |
| 969 | {0x87C, "OFM_REGION"}, |
| 970 | {0x880, "KERNEL_WIDTH_M1"}, |
| 971 | {0x884, "KERNEL_HEIGHT_M1"}, |
| 972 | {0x888, "KERNEL_STRIDE"}, |
| 973 | {0x88C, "PARALLEL_MODE"}, |
| 974 | {0x890, "ACC_FORMAT"}, |
| 975 | {0x894, "ACTIVATION"}, |
| 976 | {0x898, "ACTIVATION_MIN"}, |
| 977 | {0x89C, "ACTIVATION_MAX"}, |
| 978 | {0x8A0, "WEIGHT_REGION"}, |
| 979 | {0x8A4, "SCALE_REGION"}, |
| 980 | {0x8B4, "AB_START"}, |
| 981 | {0x8BC, "BLOCKDEP"}, |
| 982 | {0x8C0, "DMA0_SRC_REGION"}, |
| 983 | {0x8C4, "DMA0_DST_REGION"}, |
| 984 | {0x8C8, "DMA0_SIZE0"}, |
| 985 | {0x8CC, "DMA0_SIZE1"}, |
| 986 | {0x900, "IFM2_BROADCAST"}, |
| 987 | {0x904, "IFM2_SCALAR"}, |
| 988 | {0x924, "IFM2_ZERO_POINT"}, |
| 989 | {0x928, "IFM2_WIDTH0_M1"}, |
| 990 | {0x92C, "IFM2_HEIGHT0_M1"}, |
| 991 | {0x930, "IFM2_HEIGHT1_M1"}, |
| 992 | {0x934, "IFM2_IB_START"}, |
| 993 | {0x93C, "IFM2_REGION"}, |
| 994 | {0xA00, "IFM_BASE0"}, |
| 995 | {0xA04, "IFM_BASE0_HI"}, |
| 996 | {0xA08, "IFM_BASE1"}, |
| 997 | {0xA0C, "IFM_BASE1_HI"}, |
| 998 | {0xA10, "IFM_BASE2"}, |
| 999 | {0xA14, "IFM_BASE2_HI"}, |
| 1000 | {0xA18, "IFM_BASE3"}, |
| 1001 | {0xA1C, "IFM_BASE3_HI"}, |
| 1002 | {0xA20, "IFM_STRIDE_X"}, |
| 1003 | {0xA24, "IFM_STRIDE_X_HI"}, |
| 1004 | {0xA28, "IFM_STRIDE_Y"}, |
| 1005 | {0xA2C, "IFM_STRIDE_Y_HI"}, |
| 1006 | {0xA30, "IFM_STRIDE_C"}, |
| 1007 | {0xA34, "IFM_STRIDE_C_HI"}, |
| 1008 | {0xA40, "OFM_BASE0"}, |
| 1009 | {0xA44, "OFM_BASE0_HI"}, |
| 1010 | {0xA48, "OFM_BASE1"}, |
| 1011 | {0xA4C, "OFM_BASE1_HI"}, |
| 1012 | {0xA50, "OFM_BASE2"}, |
| 1013 | {0xA54, "OFM_BASE2_HI"}, |
| 1014 | {0xA58, "OFM_BASE3"}, |
| 1015 | {0xA5C, "OFM_BASE3_HI"}, |
| 1016 | {0xA60, "OFM_STRIDE_X"}, |
| 1017 | {0xA64, "OFM_STRIDE_X_HI"}, |
| 1018 | {0xA68, "OFM_STRIDE_Y"}, |
| 1019 | {0xA6C, "OFM_STRIDE_Y_HI"}, |
| 1020 | {0xA70, "OFM_STRIDE_C"}, |
| 1021 | {0xA74, "OFM_STRIDE_C_HI"}, |
| 1022 | {0xA80, "WEIGHT_BASE"}, |
| 1023 | {0xA84, "WEIGHT_BASE_HI"}, |
| 1024 | {0xA88, "WEIGHT_LENGTH"}, |
| 1025 | {0xA8C, "WEIGHT_LENGTH_HI"}, |
| 1026 | {0xA90, "SCALE_BASE"}, |
| 1027 | {0xA94, "SCALE_BASE_HI"}, |
| 1028 | {0xA98, "SCALE_LENGTH"}, |
| 1029 | {0xAA0, "OFM_SCALE"}, |
| 1030 | {0xAA4, "OFM_SCALE_SHIFT"}, |
| 1031 | {0xAA8, "OPA_SCALE "}, |
| 1032 | {0xAB0, "OPB_SCALE"}, |
| 1033 | {0xAC0, "DMA0_SRC"}, |
| 1034 | {0xAC4, "DMA0_SRC_HI"}, |
| 1035 | {0xAC8, "DMA0_DST"}, |
| 1036 | {0xACC, "DMA0_DST_HI"}, |
| 1037 | {0xAD0, "DMA0_LEN"}, |
| 1038 | {0xAD4, "DMA0_LEN_HI"}, |
| 1039 | {0xAD8, "DMA0_SKIP0"}, |
| 1040 | {0xADC, "DMA0_SKIP0_HI"}, |
| 1041 | {0xAE0, "DMA0_SKIP1"}, |
| 1042 | {0xAE4, "DMA0_SKIP1_HI"}, |
| 1043 | {0xB00, "IFM2_BASE0"}, |
| 1044 | {0xB04, "IFM2_BASE0_HI"}, |
| 1045 | {0xB08, "IFM2_BASE1"}, |
| 1046 | {0xB0C, "IFM2_BASE1_HI"}, |
| 1047 | {0xB10, "IFM2_BASE2"}, |
| 1048 | {0xB14, "IFM2_BASE2_HI"}, |
| 1049 | {0xB18, "IFM2_BASE3"}, |
| 1050 | {0xB1C, "IFM2_BASE3_HI"}, |
| 1051 | {0xB20, "IFM2_STRIDE_X"}, |
| 1052 | {0xB24, "IFM2_STRIDE_X_HI"}, |
| 1053 | {0xB28, "IFM2_STRIDE_Y"}, |
| 1054 | {0xB2C, "IFM2_STRIDE_Y_HI"}, |
| 1055 | {0xB30, "IFM2_STRIDE_C"}, |
| 1056 | {0xB34, "IFM2_STRIDE_C_HI"}, |
| 1057 | {0xB40, "WEIGHT1_BASE"}, |
| 1058 | {0xB44, "WEIGHT1_BASE_HI"}, |
| 1059 | {0xB48, "WEIGHT1_LENGTH"}, |
| 1060 | {0xB4C, "WEIGHT1_LENGTH_HI"}, |
| 1061 | {0xB50, "SCALE1_BASE"}, |
| 1062 | {0xB54, "SCALE1_BASE_HI"}, |
| 1063 | {0xB58, "SCALE1_LENGTH"}, |
| 1064 | }; |
| 1065 | |
| 1066 | static const char *lookup_name(const name_lookup_t *lookup_table, int lookup_table_count, int find) |
| 1067 | { |
| 1068 | int n; |
| 1069 | for (n = 0; n < lookup_table_count; n++) |
| 1070 | { |
| 1071 | if (lookup_table[n].number == find) |
| 1072 | { |
| 1073 | return lookup_table[n].name; |
| 1074 | } |
| 1075 | } |
| 1076 | // Not found |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 1080 | static void dump_npu_register(struct ethosu_driver *drv, int npu_reg, int npu_reg_end) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1081 | { |
| 1082 | unsigned int reg_val; |
| 1083 | const char *reg_name; |
| 1084 | int npu_reg_name_tbl_count = sizeof(npu_reg_name_tbl) / sizeof(npu_reg_name_tbl[0]); |
| 1085 | |
| 1086 | LOG_INFO("dump_register %X - %X\n", npu_reg, npu_reg_end); |
| 1087 | for (; npu_reg <= npu_reg_end; npu_reg += sizeof(int)) |
| 1088 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 1089 | reg_val = ethosu_read_reg(&drv->dev, npu_reg); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1090 | reg_name = lookup_name(npu_reg_name_tbl, npu_reg_name_tbl_count, npu_reg); |
| 1091 | LOG_INFO("[0x%.4X] 0x%.8X\t%s\n", npu_reg, reg_val, (reg_name) ? reg_name : ""); |
| 1092 | } |
| 1093 | } |
| 1094 | |
| 1095 | static const name_lookup_t cmd0_name_tbl[] = { |
| 1096 | {0x000, "NPU_OP_STOP"}, |
| 1097 | {0x001, "NPU_OP_IRQ"}, |
| 1098 | {0x002, "NPU_OP_CONV"}, |
| 1099 | {0x003, "NPU_OP_DEPTHWISE"}, |
| 1100 | {0x004, "NPU_OP_VECTOR_PROD"}, |
| 1101 | {0x005, "NPU_OP_POOL"}, |
| 1102 | {0x006, "NPU_OP_ELEMENTWISE"}, |
| 1103 | {0x010, "NPU_OP_DMA_START"}, |
| 1104 | {0x011, "NPU_OP_DMA_WAIT"}, |
| 1105 | {0x012, "NPU_OP_KERNEL_WAIT"}, |
| 1106 | {0x100, "NPU_SET_IFM_PAD_TOP"}, |
| 1107 | {0x101, "NPU_SET_IFM_PAD_LEFT"}, |
| 1108 | {0x102, "NPU_SET_IFM_PAD_RIGHT"}, |
| 1109 | {0x103, "NPU_SET_IFM_PAD_BOTTOM"}, |
| 1110 | {0x104, "NPU_SET_IFM_DEPTH_M1"}, |
| 1111 | {0x105, "NPU_SET_IFM_PRECISION"}, |
| 1112 | {0x107, "NPU_SET_IFM_UPSCALE"}, |
| 1113 | {0x109, "NPU_SET_IFM_ZERO_POINT"}, |
| 1114 | {0x10A, "NPU_SET_IFM_WIDTH0_M1"}, |
| 1115 | {0x10B, "NPU_SET_IFM_HEIGHT0_M1"}, |
| 1116 | {0x10C, "NPU_SET_IFM_HEIGHT1_M1"}, |
| 1117 | {0x10D, "NPU_SET_IFM_IB_END"}, |
| 1118 | {0x10F, "NPU_SET_IFM_REGION"}, |
| 1119 | {0x110, "NPU_SET_OFM_BATCH_SIZE_M1"}, |
| 1120 | {0x111, "NPU_SET_OFM_WIDTH_M1"}, |
| 1121 | {0x112, "NPU_SET_OFM_HEIGHT_M1"}, |
| 1122 | {0x113, "NPU_SET_OFM_DEPTH_M1"}, |
| 1123 | {0x114, "NPU_SET_OFM_PRECISION"}, |
| 1124 | {0x115, "NPU_SET_OFM_BLK_WIDTH_M1"}, |
| 1125 | {0x116, "NPU_SET_OFM_BLK_HEIGHT_M1"}, |
| 1126 | {0x117, "NPU_SET_OFM_BLK_DEPTH_M1"}, |
| 1127 | {0x118, "NPU_SET_OFM_ZERO_POINT"}, |
| 1128 | {0x11A, "NPU_SET_OFM_WIDTH0_M1"}, |
| 1129 | {0x11B, "NPU_SET_OFM_HEIGHT0_M1"}, |
| 1130 | {0x11C, "NPU_SET_OFM_HEIGHT1_M1"}, |
| 1131 | {0x11F, "NPU_SET_OFM_REGION"}, |
| 1132 | {0x120, "NPU_SET_KERNEL_WIDTH_M1"}, |
| 1133 | {0x121, "NPU_SET_KERNEL_HEIGHT_M1"}, |
| 1134 | {0x122, "NPU_SET_KERNEL_STRIDE"}, |
| 1135 | {0x124, "NPU_SET_ACC_FORMAT"}, |
| 1136 | {0x125, "NPU_SET_ACTIVATION"}, |
| 1137 | {0x126, "NPU_SET_ACTIVATION_MIN"}, |
| 1138 | {0x127, "NPU_SET_ACTIVATION_MAX"}, |
| 1139 | {0x128, "NPU_SET_WEIGHT_REGION"}, |
| 1140 | {0x129, "NPU_SET_SCALE_REGION"}, |
| 1141 | {0x12D, "NPU_SET_AB_START"}, |
| 1142 | {0x12F, "NPU_SET_BLOCKDEP"}, |
| 1143 | {0x130, "NPU_SET_DMA0_SRC_REGION"}, |
| 1144 | {0x131, "NPU_SET_DMA0_DST_REGION"}, |
| 1145 | {0x180, "NPU_SET_IFM2_BROADCAST"}, |
| 1146 | {0x181, "NPU_SET_IFM2_SCALAR"}, |
| 1147 | {0x185, "NPU_SET_IFM2_PRECISION"}, |
| 1148 | {0x189, "NPU_SET_IFM2_ZERO_POINT"}, |
| 1149 | {0x18A, "NPU_SET_IFM2_WIDTH0_M1"}, |
| 1150 | {0x18B, "NPU_SET_IFM2_HEIGHT0_M1"}, |
| 1151 | {0x18C, "NPU_SET_IFM2_HEIGHT1_M1"}, |
| 1152 | {0x18D, "NPU_SET_IFM2_IB_START"}, |
| 1153 | {0x18F, "NPU_SET_IFM2_REGION"}, |
| 1154 | }; |
| 1155 | |
| 1156 | static const name_lookup_t cmd1_name_tbl[] = { |
| 1157 | {0x000, "NPU_SET_IFM_BASE0"}, {0x001, "NPU_SET_IFM_BASE1"}, {0x002, "NPU_SET_IFM_BASE2"}, |
| 1158 | {0x003, "NPU_SET_IFM_BASE3"}, {0x004, "NPU_SET_IFM_STRIDE_X"}, {0x005, "NPU_SET_IFM_STRIDE_Y"}, |
| 1159 | {0x006, "NPU_SET_IFM_STRIDE_C"}, {0x007, "NPU_SET_IFM_STRIDE_N"}, {0x010, "NPU_SET_OFM_BASE0"}, |
| 1160 | {0x011, "NPU_SET_OFM_BASE1"}, {0x012, "NPU_SET_OFM_BASE2"}, {0x013, "NPU_SET_OFM_BASE3"}, |
| 1161 | {0x014, "NPU_SET_OFM_STRIDE_X"}, {0x015, "NPU_SET_OFM_STRIDE_Y"}, {0x016, "NPU_SET_OFM_STRIDE_C"}, |
| 1162 | {0x017, "NPU_SET_OFM_STRIDE_N"}, {0x020, "NPU_SET_WEIGHT_BASE"}, {0x021, "NPU_SET_WEIGHT_LENGTH"}, |
| 1163 | {0x022, "NPU_SET_SCALE_BASE"}, {0x023, "NPU_SET_SCALE_LENGTH"}, {0x024, "NPU_SET_OFM_SCALE"}, |
| 1164 | {0x025, "NPU_SET_OPA_SCALE"}, {0x026, "NPU_SET_OPB_SCALE"}, {0x030, "NPU_SET_DMA0_SRC"}, |
| 1165 | {0x031, "NPU_SET_DMA0_DST"}, {0x032, "NPU_SET_DMA0_LEN"}, {0x080, "NPU_SET_IFM2_BASE0"}, |
| 1166 | {0x081, "NPU_SET_IFM2_BASE1"}, {0x082, "NPU_SET_IFM2_BASE2"}, {0x083, "NPU_SET_IFM2_BASE3"}, |
| 1167 | {0x084, "NPU_SET_IFM2_STRIDE_X"}, {0x085, "NPU_SET_IFM2_STRIDE_Y"}, {0x086, "NPU_SET_IFM2_STRIDE_C"}, |
| 1168 | }; |
| 1169 | |
| 1170 | static void dump_command_stream(const uint32_t *cmd_stream, const int cms_length, int qread) |
| 1171 | { |
| 1172 | int n; |
| 1173 | int offset; |
| 1174 | uint32_t cmd_val; |
| 1175 | const uint8_t *cmd_ptr; |
| 1176 | const char *cmd_name; |
| 1177 | int cmd0_name_tbl_count = sizeof(cmd0_name_tbl) / sizeof(cmd0_name_tbl[0]); |
| 1178 | int cmd1_name_tbl_count = sizeof(cmd1_name_tbl) / sizeof(cmd1_name_tbl[0]); |
| 1179 | |
| 1180 | LOG_INFO("dump_command_stream cmd_stream = 0x%8p cms_length = %d\n", cmd_stream, cms_length); |
| 1181 | for (n = 0; n < cms_length; n++) |
| 1182 | { |
| 1183 | // Offset |
| 1184 | offset = n * sizeof(int); |
| 1185 | LOG_INFO("[%.4d] ", offset); |
| 1186 | // Command |
| 1187 | cmd_ptr = (const uint8_t *)&cmd_stream[n]; |
| 1188 | LOG_INFO("0x%.2X 0x%.2X 0x%.2X 0x%.2X ", cmd_ptr[0], cmd_ptr[1], cmd_ptr[2], cmd_ptr[3]); |
| 1189 | // Command name and payload |
| 1190 | if (cmd_stream[n] & 0x4000) |
| 1191 | { |
| 1192 | cmd_name = lookup_name(cmd1_name_tbl, cmd1_name_tbl_count, cmd_stream[n] & 0x3FF); |
| 1193 | n++; |
| 1194 | cmd_val = cmd_stream[n]; |
| 1195 | cmd_ptr = (const uint8_t *)&cmd_stream[n]; |
| 1196 | LOG_INFO("0x%.2X 0x%.2X 0x%.2X 0x%.2X ", cmd_ptr[0], cmd_ptr[1], cmd_ptr[2], cmd_ptr[3]); |
| 1197 | } |
| 1198 | else |
| 1199 | { |
| 1200 | cmd_val = cmd_stream[n] >> 16; |
| 1201 | cmd_name = lookup_name(cmd0_name_tbl, cmd0_name_tbl_count, cmd_stream[n] & 0x3FF); |
| 1202 | } |
| 1203 | if (cmd_name) |
| 1204 | { |
Per Åstrand | 14ccfee | 2020-09-25 10:40:20 +0200 | [diff] [blame] | 1205 | LOG_INFO("\t%s 0x%.8" PRIX32, cmd_name, cmd_val); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1206 | } |
| 1207 | if (offset == qread) |
| 1208 | { |
| 1209 | LOG_INFO(" <<== QREAD\n"); |
| 1210 | } |
| 1211 | else |
| 1212 | { |
| 1213 | LOG_INFO("\n"); |
| 1214 | } |
| 1215 | } |
| 1216 | } |