Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /***************************************************************************** |
| 20 | * Includes |
| 21 | *****************************************************************************/ |
| 22 | |
| 23 | #include "ethosu55_interface.h" |
| 24 | #include "ethosu_common.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 25 | #include "ethosu_driver.h" |
| 26 | #include "pmu_ethosu.h" |
| 27 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 28 | #include <assert.h> |
Per Åstrand | e07b1f9 | 2020-09-28 08:31:46 +0200 | [diff] [blame^] | 29 | #include <inttypes.h> |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 30 | #include <stddef.h> |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 31 | |
| 32 | /***************************************************************************** |
| 33 | * Defines |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | #define COMMA , |
| 37 | #define SEMICOLON ; |
| 38 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 39 | #define EVTYPE(A, name) \ |
| 40 | case PMU_EVENT_TYPE_##name: \ |
| 41 | return ETHOSU_PMU_##name |
| 42 | |
| 43 | #define EVID(A, name) (PMU_EVENT_TYPE_##name) |
| 44 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 45 | #define ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK (0x3FF) |
| 46 | |
| 47 | #define NPU_REG_PMEVCNTR(x) (NPU_REG_PMEVCNTR0 + ((x) * sizeof(uint32_t))) |
| 48 | #define NPU_REG_PMEVTYPER(x) (NPU_REG_PMEVTYPER0 + ((x) * sizeof(uint32_t))) |
| 49 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 50 | /***************************************************************************** |
| 51 | * Variables |
| 52 | *****************************************************************************/ |
| 53 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 54 | /** |
| 55 | * NOTE: A pointer to ethosu_driver will be added to the PMU functions |
| 56 | * when multi-NPU functionality is implemented later. We shall use a |
| 57 | * shared ethosu_driver instance till then. |
| 58 | * */ |
| 59 | extern struct ethosu_driver ethosu_drv; |
| 60 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 61 | static const enum pmu_event_type eventbyid[] = {EXPAND_PMU_EVENT_TYPE(EVID, COMMA)}; |
| 62 | |
| 63 | /***************************************************************************** |
| 64 | * Functions |
| 65 | *****************************************************************************/ |
| 66 | |
| 67 | enum ethosu_pmu_event_type pmu_event_type(uint32_t id) |
| 68 | { |
| 69 | switch (id) |
| 70 | { |
| 71 | EXPAND_PMU_EVENT_TYPE(EVTYPE, SEMICOLON); |
Per Åstrand | e07b1f9 | 2020-09-28 08:31:46 +0200 | [diff] [blame^] | 72 | default: |
| 73 | LOG_ERR("Unknown PMU event id: 0x%" PRIx32 "\n", id); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | return ETHOSU_PMU_SENTINEL; |
| 77 | } |
| 78 | |
| 79 | uint32_t pmu_event_value(enum ethosu_pmu_event_type event) |
| 80 | { |
| 81 | if (!(event < ETHOSU_PMU_SENTINEL) || (event < 0)) |
| 82 | { |
| 83 | return (uint32_t)(-1); |
| 84 | } |
| 85 | |
| 86 | return eventbyid[event]; |
| 87 | } |
| 88 | |
| 89 | void ethosu_pmu_driver_init(void) |
| 90 | { |
| 91 | #ifdef PMU_AUTOINIT |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 92 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, INIT_PMCR); |
| 93 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET, INIT_PMCNTENSET); |
| 94 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENCLR, INIT_PMCNTENCLR); |
| 95 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSSET, INIT_PMOVSSET); |
| 96 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSCLR, INIT_PMOVSCLR); |
| 97 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTSET, INIT_PMINTSET); |
| 98 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTCLR, INIT_PMINTCLR); |
| 99 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, INIT_PMCCNTR); |
| 100 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, INIT_PMCCNTR); |
| 101 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, INIT_PMCCNTR_CFG); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 102 | |
| 103 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 104 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 105 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i), 0); |
| 106 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(i), 0); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 107 | } |
| 108 | #endif |
| 109 | } |
| 110 | |
| 111 | void ethosu_pmu_driver_exit(void) {} |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 112 | |
| 113 | void ETHOSU_PMU_Enable(void) |
| 114 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 115 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 116 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 117 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 118 | pmcr.cnt_en = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 119 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 120 | ethosu_drv.dev.pmcr = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | void ETHOSU_PMU_Disable(void) |
| 124 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 125 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 126 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 127 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 128 | pmcr.cnt_en = 0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 129 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 130 | ethosu_drv.dev.pmcr = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | void ETHOSU_PMU_Set_EVTYPER(uint32_t num, enum ethosu_pmu_event_type type) |
| 134 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 135 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 136 | uint32_t val = pmu_event_value(type); |
| 137 | LOG_DEBUG("%s: num=%u, type=%d, val=%u\n", __FUNCTION__, num, type, val); |
| 138 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(num), val); |
| 139 | ethosu_drv.dev.pmu_evtypr[num] = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(num)); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(uint32_t num) |
| 143 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 144 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 145 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVTYPER(num)); |
| 146 | enum ethosu_pmu_event_type type = pmu_event_type(val); |
| 147 | LOG_DEBUG("%s: num=%u, type=%d, val=%u\n", __FUNCTION__, num, type, val); |
| 148 | return type; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | void ETHOSU_PMU_CYCCNT_Reset(void) |
| 152 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 153 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 154 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 155 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 156 | pmcr.cycle_cnt_rst = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 157 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Kristofer Jonsson | 77514da | 2020-09-23 08:46:41 +0200 | [diff] [blame] | 158 | ethosu_drv.dev.pmcr = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
| 159 | ethosu_drv.dev.pmccntr = 0; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | void ETHOSU_PMU_EVCNTR_ALL_Reset(void) |
| 163 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 164 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 165 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 166 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 167 | pmcr.event_cnt_rst = 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 168 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 169 | ethosu_drv.dev.pmcr = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCR); |
| 170 | |
| 171 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 172 | { |
| 173 | ethosu_drv.dev.pmu_evcntr[i] = 0; |
| 174 | } |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | void ETHOSU_PMU_CNTR_Enable(uint32_t mask) |
| 178 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 179 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 180 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET, mask); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 181 | ethosu_drv.dev.pmcnten = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | void ETHOSU_PMU_CNTR_Disable(uint32_t mask) |
| 185 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 186 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 187 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCNTENCLR, mask); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 188 | ethosu_drv.dev.pmcnten = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 189 | } |
| 190 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 191 | uint32_t ETHOSU_PMU_CNTR_Status(void) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 192 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 193 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCNTENSET); |
| 194 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, val); |
| 195 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | uint64_t ETHOSU_PMU_Get_CCNTR(void) |
| 199 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 200 | uint64_t val = (((uint64_t)ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI)) << 32) | |
| 201 | ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 202 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 203 | LOG_DEBUG("%s: val=%llu, pmccntr=%llu\n", __FUNCTION__, val, ethosu_drv.dev.pmccntr); |
| 204 | |
| 205 | // Return the cached value in case the NPU was powered off |
| 206 | if (ethosu_drv.dev.pmccntr > val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 207 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 208 | return ethosu_drv.dev.pmccntr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 209 | } |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 210 | |
| 211 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | void ETHOSU_PMU_Set_CCNTR(uint64_t val) |
| 215 | { |
| 216 | uint32_t mask = ETHOSU_PMU_CNTR_Status(); |
| 217 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 218 | LOG_DEBUG("%s: val=%llu\n", __FUNCTION__, val); |
| 219 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 220 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 221 | { |
| 222 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 223 | } |
| 224 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 225 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS)); |
| 226 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 227 | |
| 228 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 229 | { |
| 230 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 231 | } |
| 232 | } |
| 233 | |
| 234 | uint32_t ETHOSU_PMU_Get_EVCNTR(uint32_t num) |
| 235 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 236 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 237 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(num)); |
| 238 | LOG_DEBUG("%s: num=%u, val=%u, pmu_evcntr=%u\n", __FUNCTION__, num, val, ethosu_drv.dev.pmu_evcntr[num]); |
| 239 | |
| 240 | // Return the cached value in case the NPU was powered off |
| 241 | if (ethosu_drv.dev.pmu_evcntr[num] > val) |
| 242 | { |
| 243 | return ethosu_drv.dev.pmu_evcntr[num]; |
| 244 | } |
| 245 | |
| 246 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | void ETHOSU_PMU_Set_EVCNTR(uint32_t num, uint32_t val) |
| 250 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 251 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 252 | LOG_DEBUG("%s: num=%u, val=%u\n", __FUNCTION__, num, val); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 253 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(num), val); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | uint32_t ETHOSU_PMU_Get_CNTR_OVS(void) |
| 257 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 258 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 259 | return ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMOVSSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | // TODO: check if this function name match with the description & |
| 263 | // implementation. |
| 264 | void ETHOSU_PMU_Set_CNTR_OVS(uint32_t mask) |
| 265 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 266 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 267 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSCLR, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | void ETHOSU_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) |
| 271 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 272 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 273 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTSET, mask); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 274 | ethosu_drv.dev.pmint = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMINTSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) |
| 278 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 279 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 280 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMINTCLR, mask); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 281 | ethosu_drv.dev.pmint = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMINTSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 282 | } |
| 283 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 284 | uint32_t ETHOSU_PMU_Get_IRQ_Enable(void) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 285 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 286 | uint32_t mask = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMINTSET); |
| 287 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
| 288 | return mask; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 289 | } |
| 290 | |
| 291 | void ETHOSU_PMU_CNTR_Increment(uint32_t mask) |
| 292 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 293 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 294 | uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(); |
| 295 | |
| 296 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 297 | { |
| 298 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 299 | { |
| 300 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 301 | uint64_t val = ETHOSU_PMU_Get_CCNTR() + 1; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 302 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, (val & MASK_0_31_BITS)); |
| 303 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 304 | if (cntrs_active & ETHOSU_PMU_CCNT_Msk) |
| 305 | { |
| 306 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 307 | } |
| 308 | } |
| 309 | } |
| 310 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 311 | { |
| 312 | uint32_t cntr = (0x0001 << i); |
| 313 | |
| 314 | if (mask & cntr) |
| 315 | { |
| 316 | ETHOSU_PMU_CNTR_Disable(cntr); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 317 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i)); |
| 318 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(i), val + 1); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 319 | if (cntrs_active & cntr) |
| 320 | { |
| 321 | ETHOSU_PMU_CNTR_Enable(cntr); |
| 322 | } |
| 323 | } |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(uint32_t start_event) |
| 328 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 329 | LOG_DEBUG("%s: start_event=%u\n", __FUNCTION__, start_event); |
| 330 | struct pmccntr_cfg_r *cfg = (struct pmccntr_cfg_r *)ðosu_drv.dev.pmccntr_cfg; |
| 331 | cfg->CYCLE_CNT_CFG_START = start_event & ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK; |
| 332 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg->word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 333 | } |
| 334 | |
| 335 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(uint32_t stop_event) |
| 336 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 337 | LOG_DEBUG("%s: stop_event=%u\n", __FUNCTION__, stop_event); |
| 338 | struct pmccntr_cfg_r *cfg = (struct pmccntr_cfg_r *)ðosu_drv.dev.pmccntr_cfg; |
| 339 | cfg->CYCLE_CNT_CFG_STOP = stop_event & ETHOSU_PMCCNTR_CFG_START_STOP_EVENT_MASK; |
| 340 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg->word); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 341 | } |