Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 18 | #include "ethosu_device.h" |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 19 | #include "ethosu_common.h" |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 20 | #include "ethosu_config.h" |
Bhavik Patel | 790ef36 | 2020-06-03 10:05:28 +0200 | [diff] [blame] | 21 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 22 | #include <assert.h> |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 23 | #include <stddef.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 24 | #include <stdio.h> |
| 25 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 26 | #define BASEP_OFFSET 4 |
| 27 | #define REG_OFFSET 4 |
| 28 | #define BYTES_1KB 1024 |
| 29 | |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 30 | #define ADDRESS_BITS 48 |
| 31 | #define ADDRESS_MASK ((1ull << ADDRESS_BITS) - 1) |
| 32 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 33 | #if defined(ARM_NPU_STUB) |
| 34 | static uint32_t stream_length = 0; |
| 35 | #endif |
| 36 | |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 37 | enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev, |
| 38 | const void *base_address, |
| 39 | uint32_t secure_enable, |
| 40 | uint32_t privilege_enable) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 41 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 42 | #if !defined(ARM_NPU_STUB) |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 43 | dev->base_address = (volatile uint32_t *)base_address; |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 44 | dev->secure = secure_enable; |
| 45 | dev->privileged = privilege_enable; |
| 46 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 47 | ethosu_save_pmu_config(dev); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 48 | #else |
| 49 | UNUSED(dev); |
| 50 | UNUSED(base_address); |
| 51 | #endif |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 52 | return ETHOSU_SUCCESS; |
| 53 | } |
| 54 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 55 | enum ethosu_error_codes ethosu_get_id(struct ethosu_device *dev, struct ethosu_id *id) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 56 | { |
| 57 | struct id_r _id; |
| 58 | |
| 59 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 60 | _id.word = ethosu_read_reg(dev, NPU_REG_ID); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 61 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 62 | UNUSED(dev); |
| 63 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 64 | _id.word = 0; |
| 65 | _id.arch_patch_rev = NNX_ARCH_VERSION_PATCH; |
| 66 | _id.arch_minor_rev = NNX_ARCH_VERSION_MINOR; |
| 67 | _id.arch_major_rev = NNX_ARCH_VERSION_MAJOR; |
| 68 | #endif |
| 69 | |
| 70 | id->version_status = _id.version_status; |
| 71 | id->version_minor = _id.version_minor; |
| 72 | id->version_major = _id.version_major; |
| 73 | id->product_major = _id.product_major; |
| 74 | id->arch_patch_rev = _id.arch_patch_rev; |
| 75 | id->arch_minor_rev = _id.arch_minor_rev; |
| 76 | id->arch_major_rev = _id.arch_major_rev; |
| 77 | |
| 78 | return ETHOSU_SUCCESS; |
| 79 | } |
| 80 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 81 | enum ethosu_error_codes ethosu_get_config(struct ethosu_device *dev, struct ethosu_config *config) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 82 | { |
| 83 | struct config_r cfg = {.word = 0}; |
| 84 | |
| 85 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 86 | cfg.word = ethosu_read_reg(dev, NPU_REG_CONFIG); |
| 87 | #else |
| 88 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 89 | #endif |
| 90 | |
| 91 | config->macs_per_cc = cfg.macs_per_cc; |
| 92 | config->cmd_stream_version = cfg.cmd_stream_version; |
| 93 | config->shram_size = cfg.shram_size; |
| 94 | |
| 95 | return ETHOSU_SUCCESS; |
| 96 | } |
| 97 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 98 | enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev, |
| 99 | const uint8_t *cmd_stream_ptr, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 100 | uint32_t cms_length, |
| 101 | const uint64_t *base_addr, |
| 102 | int num_base_addr) |
| 103 | { |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 104 | enum ethosu_error_codes ret_code = ETHOSU_SUCCESS; |
| 105 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 106 | #if !defined(ARM_NPU_STUB) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 107 | ASSERT(num_base_addr <= ETHOSU_DRIVER_BASEP_INDEXES); |
| 108 | |
Per Åstrand | c6c1db1 | 2020-09-28 08:41:45 +0200 | [diff] [blame] | 109 | uint64_t qbase = (uintptr_t)cmd_stream_ptr + BASE_POINTER_OFFSET; |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 110 | ASSERT(qbase <= ADDRESS_MASK); |
| 111 | LOG_DEBUG("QBASE=0x%016llx, QSIZE=%u, base_pointer_offset=0x%08x\n", qbase, cms_length, BASE_POINTER_OFFSET); |
| 112 | ethosu_write_reg(dev, NPU_REG_QBASE0, qbase & 0xffffffff); |
| 113 | ethosu_write_reg(dev, NPU_REG_QBASE1, qbase >> 32); |
| 114 | ethosu_write_reg(dev, NPU_REG_QSIZE, cms_length); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 115 | |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 116 | for (int i = 0; i < num_base_addr; i++) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 117 | { |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 118 | uint64_t addr = base_addr[i] + BASE_POINTER_OFFSET; |
| 119 | ASSERT(addr <= ADDRESS_MASK); |
| 120 | LOG_DEBUG("BASEP%d=0x%016llx\n", i, addr); |
| 121 | ethosu_write_reg(dev, NPU_REG_BASEP0 + (2 * i) * BASEP_OFFSET, addr & 0xffffffff); |
| 122 | ethosu_write_reg(dev, NPU_REG_BASEP0 + (2 * i + 1) * BASEP_OFFSET, addr >> 32); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 123 | } |
| 124 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 125 | ret_code = ethosu_set_command_run(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 126 | #else |
| 127 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 128 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 129 | stream_length = cms_length; |
| 130 | UNUSED(cmd_stream_ptr); |
| 131 | UNUSED(base_addr); |
| 132 | ASSERT(num_base_addr < ETHOSU_DRIVER_BASEP_INDEXES); |
| 133 | #if defined(NDEBUG) |
| 134 | UNUSED(num_base_addr); |
| 135 | #endif |
| 136 | #endif |
| 137 | |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 138 | return ret_code; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 139 | } |
| 140 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 141 | enum ethosu_error_codes ethosu_is_irq_raised(struct ethosu_device *dev, uint8_t *irq_raised) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 142 | { |
| 143 | #if !defined(ARM_NPU_STUB) |
| 144 | struct status_r status; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 145 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 146 | if (status.irq_raised == 1) |
| 147 | { |
| 148 | *irq_raised = 1; |
| 149 | } |
| 150 | else |
| 151 | { |
| 152 | *irq_raised = 0; |
| 153 | } |
| 154 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 155 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 156 | *irq_raised = 1; |
| 157 | #endif |
| 158 | return ETHOSU_SUCCESS; |
| 159 | } |
| 160 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 161 | enum ethosu_error_codes ethosu_clear_irq_status(struct ethosu_device *dev) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 162 | { |
| 163 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 164 | struct cmd_r oldcmd; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 165 | oldcmd.word = ethosu_read_reg(dev, NPU_REG_CMD); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 166 | struct cmd_r cmd; |
Per Åstrand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 167 | |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 168 | cmd.word = 0; |
| 169 | cmd.clear_irq = 1; |
| 170 | cmd.clock_q_enable = oldcmd.clock_q_enable; |
| 171 | cmd.power_q_enable = oldcmd.power_q_enable; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 172 | ethosu_write_reg(dev, NPU_REG_CMD, cmd.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 173 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 174 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 175 | #endif |
| 176 | return ETHOSU_SUCCESS; |
| 177 | } |
| 178 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 179 | enum ethosu_error_codes ethosu_soft_reset(struct ethosu_device *dev) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 180 | { |
| 181 | enum ethosu_error_codes return_code = ETHOSU_SUCCESS; |
| 182 | #if !defined(ARM_NPU_STUB) |
| 183 | struct reset_r reset; |
| 184 | struct prot_r prot; |
| 185 | |
| 186 | reset.word = 0; |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 187 | reset.pending_CPL = dev->privileged ? PRIVILEGE_LEVEL_PRIVILEGED : PRIVILEGE_LEVEL_USER; |
| 188 | reset.pending_CSL = dev->secure ? SECURITY_LEVEL_SECURE : SECURITY_LEVEL_NON_SECURE; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 189 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 190 | prot.word = ethosu_read_reg(dev, NPU_REG_PROT); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 191 | |
| 192 | if (prot.active_CPL < reset.pending_CPL && prot.active_CSL > reset.pending_CSL) |
| 193 | { |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 194 | LOG_ERR("Failed to reset NPU\n"); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 195 | // Register access not permitted |
| 196 | return ETHOSU_GENERIC_FAILURE; |
| 197 | } |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 198 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 199 | // Reset and set security level |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 200 | ethosu_write_reg(dev, NPU_REG_RESET, reset.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 201 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 202 | // Wait for reset to complete |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 203 | return_code = ethosu_wait_for_reset(dev); |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 204 | |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 205 | // Save the prot register |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 206 | dev->reset = ethosu_read_reg(dev, NPU_REG_PROT); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 207 | |
| 208 | // Soft reset will clear the PMU configuration and counters. The shadow PMU counters |
| 209 | // are cleared by saving the PMU counters to ram, which will read back zeros. |
| 210 | // The PMU configuration will be restored in the invoke function after power save |
| 211 | // has been disabled. |
| 212 | ethosu_save_pmu_counters(dev); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 213 | #else |
| 214 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 215 | #endif |
| 216 | |
| 217 | return return_code; |
| 218 | } |
| 219 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 220 | enum ethosu_error_codes ethosu_wait_for_reset(struct ethosu_device *dev) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 221 | { |
| 222 | #if !defined(ARM_NPU_STUB) |
| 223 | struct status_r status; |
| 224 | |
| 225 | // Wait until reset status indicates that reset has been completed |
| 226 | for (int i = 0; i < 100000; i++) |
| 227 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 228 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 229 | if (0 == status.reset_status) |
| 230 | { |
| 231 | break; |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | if (1 == status.reset_status) |
| 236 | { |
| 237 | return ETHOSU_GENERIC_FAILURE; |
| 238 | } |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 239 | #else |
| 240 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 241 | #endif |
| 242 | |
| 243 | return ETHOSU_SUCCESS; |
| 244 | } |
| 245 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 246 | enum ethosu_error_codes ethosu_read_apb_reg(struct ethosu_device *dev, |
| 247 | uint32_t start_address, |
| 248 | uint16_t num_reg, |
| 249 | uint32_t *reg) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 250 | { |
| 251 | #if !defined(ARM_NPU_STUB) |
| 252 | uint32_t address = start_address; |
| 253 | |
Douglas Troha | 2e7e3b7 | 2020-05-14 20:28:31 +0200 | [diff] [blame] | 254 | ASSERT((start_address + num_reg) < ID_REGISTERS_SIZE); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 255 | |
| 256 | for (int i = 0; i < num_reg; i++) |
| 257 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 258 | reg[i] = ethosu_read_reg(dev, address); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 259 | address += REG_OFFSET; |
| 260 | } |
| 261 | #else |
| 262 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 263 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 264 | UNUSED(start_address); |
| 265 | UNUSED(num_reg); |
| 266 | UNUSED(reg); |
| 267 | #endif |
| 268 | |
| 269 | return ETHOSU_SUCCESS; |
| 270 | } |
| 271 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 272 | enum ethosu_error_codes ethosu_set_qconfig(struct ethosu_device *dev, enum ethosu_memory_type memory_type) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 273 | { |
| 274 | if (memory_type > ETHOSU_AXI1_OUTSTANDING_COUNTER3) |
| 275 | { |
| 276 | return ETHOSU_INVALID_PARAM; |
| 277 | } |
| 278 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 279 | ethosu_write_reg(dev, NPU_REG_QCONFIG, memory_type); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 280 | #else |
| 281 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 282 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 283 | UNUSED(memory_type); |
| 284 | #endif |
| 285 | return ETHOSU_SUCCESS; |
| 286 | } |
| 287 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 288 | enum ethosu_error_codes ethosu_set_regioncfg(struct ethosu_device *dev, |
| 289 | uint8_t region, |
| 290 | enum ethosu_memory_type memory_type) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 291 | { |
| 292 | if (region > 7) |
| 293 | { |
| 294 | return ETHOSU_INVALID_PARAM; |
| 295 | } |
| 296 | #if !defined(ARM_NPU_STUB) |
| 297 | struct regioncfg_r regioncfg; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 298 | regioncfg.word = ethosu_read_reg(dev, NPU_REG_REGIONCFG); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 299 | regioncfg.word &= ~(0x3 << (2 * region)); |
| 300 | regioncfg.word |= (memory_type & 0x3) << (2 * region); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 301 | ethosu_write_reg(dev, NPU_REG_REGIONCFG, regioncfg.word); |
Kristofer Jonsson | 125429a | 2020-08-20 16:52:23 +0200 | [diff] [blame] | 302 | LOG_DEBUG("REGIONCFG%u=0x%08x\n", region, regioncfg.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 303 | #else |
| 304 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 305 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 306 | UNUSED(region); |
| 307 | UNUSED(memory_type); |
| 308 | #endif |
| 309 | return ETHOSU_SUCCESS; |
| 310 | } |
| 311 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 312 | enum ethosu_error_codes ethosu_set_axi_limit0(struct ethosu_device *dev, |
| 313 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 314 | enum ethosu_axi_limit_mem_type memtype, |
| 315 | uint8_t max_reads, |
| 316 | uint8_t max_writes) |
| 317 | { |
| 318 | #if !defined(ARM_NPU_STUB) |
| 319 | struct axi_limit0_r axi_limit0; |
Per Åstrand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 320 | axi_limit0.word = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 321 | axi_limit0.max_beats = max_beats; |
| 322 | axi_limit0.memtype = memtype; |
| 323 | axi_limit0.max_outstanding_read_m1 = max_reads - 1; |
| 324 | axi_limit0.max_outstanding_write_m1 = max_writes - 1; |
| 325 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 326 | ethosu_write_reg(dev, NPU_REG_AXI_LIMIT0, axi_limit0.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 327 | #else |
| 328 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 329 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 330 | UNUSED(max_beats); |
| 331 | UNUSED(memtype); |
| 332 | UNUSED(max_reads); |
| 333 | UNUSED(max_writes); |
| 334 | #endif |
| 335 | |
| 336 | return ETHOSU_SUCCESS; |
| 337 | } |
| 338 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 339 | enum ethosu_error_codes ethosu_set_axi_limit1(struct ethosu_device *dev, |
| 340 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 341 | enum ethosu_axi_limit_mem_type memtype, |
| 342 | uint8_t max_reads, |
| 343 | uint8_t max_writes) |
| 344 | { |
| 345 | #if !defined(ARM_NPU_STUB) |
| 346 | struct axi_limit1_r axi_limit1; |
Per Åstrand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 347 | axi_limit1.word = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 348 | axi_limit1.max_beats = max_beats; |
| 349 | axi_limit1.memtype = memtype; |
| 350 | axi_limit1.max_outstanding_read_m1 = max_reads - 1; |
| 351 | axi_limit1.max_outstanding_write_m1 = max_writes - 1; |
| 352 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 353 | ethosu_write_reg(dev, NPU_REG_AXI_LIMIT1, axi_limit1.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 354 | #else |
| 355 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 356 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 357 | UNUSED(max_beats); |
| 358 | UNUSED(memtype); |
| 359 | UNUSED(max_reads); |
| 360 | UNUSED(max_writes); |
| 361 | #endif |
| 362 | |
| 363 | return ETHOSU_SUCCESS; |
| 364 | } |
| 365 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 366 | enum ethosu_error_codes ethosu_set_axi_limit2(struct ethosu_device *dev, |
| 367 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 368 | enum ethosu_axi_limit_mem_type memtype, |
| 369 | uint8_t max_reads, |
| 370 | uint8_t max_writes) |
| 371 | { |
| 372 | #if !defined(ARM_NPU_STUB) |
| 373 | struct axi_limit2_r axi_limit2; |
Per Åstrand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 374 | axi_limit2.word = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 375 | axi_limit2.max_beats = max_beats; |
| 376 | axi_limit2.memtype = memtype; |
| 377 | axi_limit2.max_outstanding_read_m1 = max_reads - 1; |
| 378 | axi_limit2.max_outstanding_write_m1 = max_writes - 1; |
| 379 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 380 | ethosu_write_reg(dev, NPU_REG_AXI_LIMIT2, axi_limit2.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 381 | #else |
| 382 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 383 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 384 | UNUSED(max_beats); |
| 385 | UNUSED(memtype); |
| 386 | UNUSED(max_reads); |
| 387 | UNUSED(max_writes); |
| 388 | #endif |
| 389 | |
| 390 | return ETHOSU_SUCCESS; |
| 391 | } |
| 392 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 393 | enum ethosu_error_codes ethosu_set_axi_limit3(struct ethosu_device *dev, |
| 394 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 395 | enum ethosu_axi_limit_mem_type memtype, |
| 396 | uint8_t max_reads, |
| 397 | uint8_t max_writes) |
| 398 | { |
| 399 | #if !defined(ARM_NPU_STUB) |
| 400 | struct axi_limit3_r axi_limit3; |
Per Åstrand | 9716b5e | 2020-08-19 13:15:06 +0200 | [diff] [blame] | 401 | axi_limit3.word = 0; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 402 | axi_limit3.max_beats = max_beats; |
| 403 | axi_limit3.memtype = memtype; |
| 404 | axi_limit3.max_outstanding_read_m1 = max_reads - 1; |
| 405 | axi_limit3.max_outstanding_write_m1 = max_writes - 1; |
| 406 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 407 | ethosu_write_reg(dev, NPU_REG_AXI_LIMIT3, axi_limit3.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 408 | #else |
| 409 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 410 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 411 | UNUSED(max_beats); |
| 412 | UNUSED(memtype); |
| 413 | UNUSED(max_reads); |
| 414 | UNUSED(max_writes); |
| 415 | #endif |
| 416 | |
| 417 | return ETHOSU_SUCCESS; |
| 418 | } |
| 419 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 420 | enum ethosu_error_codes ethosu_get_revision(struct ethosu_device *dev, uint32_t *revision) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 421 | { |
| 422 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 423 | *revision = ethosu_read_reg(dev, NPU_REG_REVISION); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 424 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 425 | UNUSED(dev); |
| 426 | *revision = 0xDEADC0DE; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 427 | #endif |
| 428 | return ETHOSU_SUCCESS; |
| 429 | } |
| 430 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 431 | enum ethosu_error_codes ethosu_get_qread(struct ethosu_device *dev, uint32_t *qread) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 432 | { |
| 433 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 434 | *qread = ethosu_read_reg(dev, NPU_REG_QREAD); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 435 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 436 | UNUSED(dev); |
| 437 | *qread = stream_length; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 438 | #endif |
| 439 | return ETHOSU_SUCCESS; |
| 440 | } |
| 441 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 442 | enum ethosu_error_codes ethosu_get_status_mask(struct ethosu_device *dev, uint16_t *status_mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 443 | { |
| 444 | #if !defined(ARM_NPU_STUB) |
| 445 | struct status_r status; |
| 446 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 447 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 448 | *status_mask = status.word & 0xFFFF; |
| 449 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 450 | UNUSED(dev); |
| 451 | *status_mask = 0x0000; |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 452 | #endif |
| 453 | return ETHOSU_SUCCESS; |
| 454 | } |
| 455 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 456 | enum ethosu_error_codes ethosu_get_irq_history_mask(struct ethosu_device *dev, uint16_t *irq_history_mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 457 | { |
| 458 | #if !defined(ARM_NPU_STUB) |
| 459 | struct status_r status; |
| 460 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 461 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 462 | *irq_history_mask = status.irq_history_mask; |
| 463 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 464 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 465 | *irq_history_mask = 0xffff; |
| 466 | #endif |
| 467 | return ETHOSU_SUCCESS; |
| 468 | } |
| 469 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 470 | enum ethosu_error_codes ethosu_clear_irq_history_mask(struct ethosu_device *dev, uint16_t irq_history_clear_mask) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 471 | { |
| 472 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 473 | struct cmd_r oldcmd; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 474 | oldcmd.word = ethosu_read_reg(dev, NPU_REG_CMD); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 475 | |
| 476 | struct cmd_r cmd; |
| 477 | cmd.word = 0; |
| 478 | cmd.clock_q_enable = oldcmd.clock_q_enable; |
| 479 | cmd.power_q_enable = oldcmd.power_q_enable; |
| 480 | cmd.clear_irq_history = irq_history_clear_mask; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 481 | ethosu_write_reg(dev, NPU_REG_CMD, cmd.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 482 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 483 | UNUSED(dev); |
Bhavik Patel | bcb5aaa | 2020-05-12 10:09:41 +0200 | [diff] [blame] | 484 | UNUSED(irq_history_clear_mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 485 | #endif |
| 486 | return ETHOSU_SUCCESS; |
| 487 | } |
| 488 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 489 | enum ethosu_error_codes ethosu_set_command_run(struct ethosu_device *dev) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 490 | { |
| 491 | #if !defined(ARM_NPU_STUB) |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 492 | struct cmd_r oldcmd; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 493 | oldcmd.word = ethosu_read_reg(dev, NPU_REG_CMD); |
Bhavik Patel | e645fed | 2020-06-12 14:46:47 +0200 | [diff] [blame] | 494 | |
| 495 | struct cmd_r cmd; |
| 496 | cmd.word = 0; |
| 497 | cmd.transition_to_running_state = 1; |
| 498 | cmd.clock_q_enable = oldcmd.clock_q_enable; |
| 499 | cmd.power_q_enable = oldcmd.power_q_enable; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 500 | ethosu_write_reg(dev, NPU_REG_CMD, cmd.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 501 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 502 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 503 | #endif |
| 504 | return ETHOSU_SUCCESS; |
| 505 | } |
| 506 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 507 | enum ethosu_error_codes ethosu_get_shram_data(struct ethosu_device *dev, int section, uint32_t *shram_p) |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 508 | { |
| 509 | #if !defined(ARM_NPU_STUB) |
| 510 | int i = 0; |
| 511 | uint32_t address = NPU_REG_SHARED_BUFFER0; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 512 | ethosu_write_reg(dev, NPU_REG_DEBUG_ADDRESS, section * BYTES_1KB); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 513 | |
| 514 | while (address <= NPU_REG_SHARED_BUFFER255) |
| 515 | { |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 516 | shram_p[i] = ethosu_read_reg(dev, address); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 517 | address += REG_OFFSET; |
| 518 | i++; |
| 519 | } |
| 520 | #else |
| 521 | // NPU stubbed |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 522 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 523 | UNUSED(section); |
| 524 | UNUSED(shram_p); |
| 525 | #endif |
| 526 | |
| 527 | return ETHOSU_SUCCESS; |
| 528 | } |
| 529 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 530 | enum ethosu_error_codes ethosu_set_clock_and_power(struct ethosu_device *dev, |
| 531 | enum ethosu_clock_q_request clock_q, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 532 | enum ethosu_power_q_request power_q) |
| 533 | { |
| 534 | #if !defined(ARM_NPU_STUB) |
| 535 | struct cmd_r cmd; |
| 536 | cmd.word = 0; |
| 537 | cmd.clock_q_enable = clock_q; |
| 538 | cmd.power_q_enable = power_q; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 539 | ethosu_write_reg(dev, NPU_REG_CMD, cmd.word); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 540 | #else |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 541 | UNUSED(dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 542 | UNUSED(clock_q); |
| 543 | UNUSED(power_q); |
| 544 | #endif |
| 545 | return ETHOSU_SUCCESS; |
| 546 | } |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 547 | |
| 548 | uint32_t ethosu_read_reg(struct ethosu_device *dev, uint32_t address) |
| 549 | { |
| 550 | #if !defined(ARM_NPU_STUB) |
Per Åstrand | c801901 | 2020-09-28 08:44:42 +0200 | [diff] [blame] | 551 | ASSERT(dev->base_address != 0); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 552 | ASSERT(address % 4 == 0); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 553 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 554 | volatile uint32_t *reg = dev->base_address + address / sizeof(uint32_t); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 555 | return *reg; |
| 556 | #else |
| 557 | UNUSED(dev); |
| 558 | UNUSED(address); |
| 559 | |
| 560 | return 0; |
| 561 | #endif |
| 562 | } |
| 563 | |
| 564 | void ethosu_write_reg(struct ethosu_device *dev, uint32_t address, uint32_t value) |
| 565 | { |
| 566 | #if !defined(ARM_NPU_STUB) |
Per Åstrand | c801901 | 2020-09-28 08:44:42 +0200 | [diff] [blame] | 567 | ASSERT(dev->base_address != 0); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 568 | ASSERT(address % 4 == 0); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 569 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 570 | volatile uint32_t *reg = dev->base_address + address / sizeof(uint32_t); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 571 | *reg = value; |
| 572 | #else |
| 573 | UNUSED(dev); |
| 574 | UNUSED(address); |
| 575 | UNUSED(value); |
| 576 | #endif |
| 577 | } |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 578 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 579 | void ethosu_write_reg_shadow(struct ethosu_device *dev, uint32_t address, uint32_t value, uint32_t *shadow) |
| 580 | { |
| 581 | ethosu_write_reg(dev, address, value); |
| 582 | *shadow = ethosu_read_reg(dev, address); |
| 583 | } |
| 584 | |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 585 | enum ethosu_error_codes ethosu_save_pmu_config(struct ethosu_device *dev) |
| 586 | { |
| 587 | #if !defined(ARM_NPU_STUB) |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 588 | // Save the PMU control register |
| 589 | dev->pmcr = ethosu_read_reg(dev, NPU_REG_PMCR); |
| 590 | |
| 591 | // Save IRQ control |
| 592 | dev->pmint = ethosu_read_reg(dev, NPU_REG_PMINTSET); |
| 593 | |
| 594 | // Save the enabled events mask |
| 595 | dev->pmcnten = ethosu_read_reg(dev, NPU_REG_PMCNTENSET); |
| 596 | |
| 597 | // Save start and stop event |
| 598 | dev->pmccntr_cfg = ethosu_read_reg(dev, NPU_REG_PMCCNTR_CFG); |
| 599 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 600 | // Save the event settings and counters |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 601 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 602 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 603 | dev->pmu_evtypr[i] = ethosu_read_reg(dev, NPU_REG_PMEVTYPER0 + i * sizeof(uint32_t)); |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 604 | } |
| 605 | #else |
| 606 | UNUSED(dev); |
| 607 | #endif |
| 608 | |
| 609 | return ETHOSU_SUCCESS; |
| 610 | } |
| 611 | |
| 612 | enum ethosu_error_codes ethosu_restore_pmu_config(struct ethosu_device *dev) |
| 613 | { |
| 614 | #if !defined(ARM_NPU_STUB) |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 615 | // Restore PMU control register |
| 616 | ethosu_write_reg(dev, NPU_REG_PMCR, dev->pmcr); |
| 617 | |
| 618 | // Restore IRQ control |
| 619 | ethosu_write_reg(dev, NPU_REG_PMINTSET, dev->pmint); |
| 620 | |
| 621 | // Restore enabled event mask |
| 622 | ethosu_write_reg(dev, NPU_REG_PMCNTENSET, dev->pmcnten); |
| 623 | |
| 624 | // Restore start and stop event |
| 625 | ethosu_write_reg(dev, NPU_REG_PMCCNTR_CFG, dev->pmccntr_cfg); |
| 626 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 627 | // Save the event settings and counters |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 628 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 629 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 630 | ethosu_write_reg(dev, NPU_REG_PMEVTYPER0 + i * sizeof(uint32_t), dev->pmu_evtypr[i]); |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 631 | } |
| 632 | #else |
| 633 | UNUSED(dev); |
| 634 | #endif |
| 635 | |
| 636 | return ETHOSU_SUCCESS; |
| 637 | } |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 638 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 639 | enum ethosu_error_codes ethosu_save_pmu_counters(struct ethosu_device *dev) |
| 640 | { |
| 641 | #if !defined(ARM_NPU_STUB) |
| 642 | // Save the cycle counter |
| 643 | dev->pmccntr[0] = ethosu_read_reg(dev, NPU_REG_PMCCNTR_LO); |
| 644 | dev->pmccntr[1] = ethosu_read_reg(dev, NPU_REG_PMCCNTR_HI); |
| 645 | |
| 646 | // Save the event settings and counters |
| 647 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 648 | { |
| 649 | dev->pmu_evcntr[i] = ethosu_read_reg(dev, NPU_REG_PMEVCNTR0 + i * sizeof(uint32_t)); |
| 650 | } |
| 651 | #else |
| 652 | UNUSED(dev); |
| 653 | #endif |
| 654 | |
| 655 | return ETHOSU_SUCCESS; |
| 656 | } |
| 657 | |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 658 | bool ethosu_status_has_error(struct ethosu_device *dev) |
| 659 | { |
| 660 | bool status_error = false; |
| 661 | #if !defined(ARM_NPU_STUB) |
| 662 | struct status_r status; |
| 663 | status.word = ethosu_read_reg(dev, NPU_REG_STATUS); |
| 664 | status_error = ((1 == status.bus_status) || (1 == status.cmd_parse_error) || (1 == status.wd_fault) || |
| 665 | (1 == status.ecc_fault)); |
| 666 | #else |
| 667 | UNUSED(dev); |
| 668 | #endif |
| 669 | return status_error; |
| 670 | } |