Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 1 | /* |
Per Åstrand | 81e01af | 2021-02-19 13:45:26 +0100 | [diff] [blame] | 2 | * Copyright (c) 2009-2021 Arm Limited. All rights reserved. |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame^] | 19 | /* |
| 20 | * This is a simplified picture of the Corstone-300 memory system. |
| 21 | * Please refer to the Corstone SSE-300 Technical Reference Manual for |
| 22 | * further information. |
| 23 | * |
| 24 | * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300 |
| 25 | * |
| 26 | * +---------------+ +---------------+ +------+ |
| 27 | * | Ethos-U55 | | Cortex-M55 +--+ ITCM | |
| 28 | * | | | | +------+ |
| 29 | * | | | | |
| 30 | * | | | | +------+ |
| 31 | * | M1 M0 | | +--+ DTCM | |
| 32 | * +---+-------+---+ +-------+-------+ +------+ |
| 33 | * | | | |
| 34 | * | +---+---------------+-----+ |
| 35 | * | | AMBA AXI NIC-400-Lite | |
| 36 | * | +---+-----------------+---+ |
| 37 | * | | | |
| 38 | * +---+-------+------------+ +--+-------+ |
| 39 | * | AMBA AXI NIC-400 | | SSE-300 | |
| 40 | * +---+--------+--------+--+ | SRAM | |
| 41 | * | | | +----------+ |
| 42 | * +---+---+ +--+---+ +--+--+ |
| 43 | * | Flash | | BRAM | | DDR | |
| 44 | * +-------+ +------+ +-----+ |
| 45 | * |
| 46 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 47 | * | Memory region name | Base addr | Size |IDAU| MCC load address + remarks | |
| 48 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 49 | * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | |
| 50 | * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | |
| 51 | * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0040_0000 | NS | 0x0040_0000; 2 MiB | |
| 52 | * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0040_0000 | S | Secure alias for NS BRAM | |
| 53 | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | |
| 54 | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | |
| 55 | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency) | |
| 56 | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S | Secure alias for NS internal SRAM | |
| 57 | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | |
| 58 | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | |
| 59 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 60 | * |
| 61 | * Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and |
| 62 | * the model should only be placed in those regions. |
| 63 | * |
| 64 | * Note: Alias regions means that secure and non-secure addresses are mapped to the same physical |
| 65 | * memory banks. |
| 66 | */ |
| 67 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 68 | __STACK_SIZE = 0x00008000; |
| 69 | __HEAP_SIZE = 0x00008000; |
| 70 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 71 | MEMORY |
| 72 | { |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 73 | ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame^] | 74 | BRAM (rw) : ORIGIN = 0x11000000, LENGTH = 0x00400000 |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 75 | DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 0x00080000 |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame^] | 76 | SRAM (rw) : ORIGIN = 0x31000000, LENGTH = 0x00200000 |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 77 | DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x60000000 |
| 78 | } |
| 79 | |
| 80 | PHDRS |
| 81 | { |
| 82 | rom_exec PT_LOAD; |
| 83 | rom_dram PT_LOAD; |
| 84 | null PT_NULL; |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | /* Linker script to place sections and symbol values. Should be used together |
| 88 | * with other linker script that defines memory regions ITCM and RAM. |
| 89 | * It references following symbols, which must be defined in code: |
| 90 | * Reset_Handler : Entry of reset handler |
| 91 | * |
| 92 | * It defines following symbols, which code can use without definition: |
| 93 | * __exidx_start |
| 94 | * __exidx_end |
| 95 | * __copy_table_start__ |
| 96 | * __copy_table_end__ |
| 97 | * __zero_table_start__ |
| 98 | * __zero_table_end__ |
| 99 | * __etext |
| 100 | * __data_start__ |
| 101 | * __preinit_array_start |
| 102 | * __preinit_array_end |
| 103 | * __init_array_start |
| 104 | * __init_array_end |
| 105 | * __fini_array_start |
| 106 | * __fini_array_end |
| 107 | * __data_end__ |
| 108 | * __bss_start__ |
| 109 | * __bss_end__ |
| 110 | * __end__ |
| 111 | * end |
| 112 | * __HeapLimit |
| 113 | * __StackLimit |
| 114 | * __StackTop |
| 115 | * __stack |
| 116 | */ |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 117 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 118 | ENTRY(Reset_Handler) |
| 119 | |
| 120 | SECTIONS |
| 121 | { |
| 122 | .text : |
| 123 | { |
| 124 | KEEP(*(.vectors)) |
| 125 | *(.text*) |
| 126 | |
| 127 | KEEP(*(.init)) |
| 128 | KEEP(*(.fini)) |
| 129 | |
| 130 | /* .ctors */ |
| 131 | *crtbegin.o(.ctors) |
| 132 | *crtbegin?.o(.ctors) |
| 133 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) |
| 134 | *(SORT(.ctors.*)) |
| 135 | *(.ctors) |
| 136 | |
| 137 | /* .dtors */ |
| 138 | *crtbegin.o(.dtors) |
| 139 | *crtbegin?.o(.dtors) |
| 140 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) |
| 141 | *(SORT(.dtors.*)) |
| 142 | *(.dtors) |
| 143 | |
| 144 | *(.rodata*) |
| 145 | |
| 146 | KEEP(*(.eh_frame*)) |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 147 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 148 | |
| 149 | /* |
| 150 | * SG veneers: |
| 151 | * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 152 | * must be set, either with the command line option '--section-start' or in a linker script, |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 153 | * to indicate where to place these veneers in memory. |
| 154 | */ |
| 155 | /* |
| 156 | .gnu.sgstubs : |
| 157 | { |
| 158 | . = ALIGN(32); |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 159 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 160 | */ |
| 161 | .ARM.extab : |
| 162 | { |
| 163 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 164 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 165 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 166 | .ARM.exidx : |
| 167 | { |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 168 | __exidx_start = .; |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 169 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 170 | __exidx_end = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 171 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 172 | |
| 173 | .copy.table : |
| 174 | { |
| 175 | . = ALIGN(4); |
| 176 | __copy_table_start__ = .; |
| 177 | LONG (__etext) |
| 178 | LONG (__data_start__) |
| 179 | LONG (__data_end__ - __data_start__) |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 180 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 181 | LONG (__eddr_data) |
| 182 | LONG (__sram_data_start__) |
| 183 | LONG (__sram_data_end__ - __sram_data_start__ ) |
| 184 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 185 | __copy_table_end__ = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 186 | } > ITCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 187 | |
| 188 | .zero.table : |
| 189 | { |
| 190 | . = ALIGN(4); |
| 191 | __zero_table_start__ = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 192 | LONG (__bss_start__) |
| 193 | LONG (__bss_end__ - __bss_start__) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 194 | __zero_table_end__ = .; |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 195 | |
| 196 | /** |
| 197 | * Location counter can end up 2byte aligned with narrow Thumb code but |
| 198 | * __etext is assumed by startup code to be the LMA of a section in DTCM |
| 199 | * which must be 4byte aligned |
| 200 | */ |
| 201 | __etext = ALIGN (4); |
| 202 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 203 | } > ITCM :rom_exec |
| 204 | |
| 205 | .data : AT(__etext) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 206 | { |
| 207 | __data_start__ = .; |
| 208 | *(vtable) |
| 209 | *(.data) |
| 210 | *(.data.*) |
| 211 | |
| 212 | . = ALIGN(4); |
| 213 | /* preinit data */ |
| 214 | PROVIDE_HIDDEN (__preinit_array_start = .); |
| 215 | KEEP(*(.preinit_array)) |
| 216 | PROVIDE_HIDDEN (__preinit_array_end = .); |
| 217 | |
| 218 | . = ALIGN(4); |
| 219 | /* init data */ |
| 220 | PROVIDE_HIDDEN (__init_array_start = .); |
| 221 | KEEP(*(SORT(.init_array.*))) |
| 222 | KEEP(*(.init_array)) |
| 223 | PROVIDE_HIDDEN (__init_array_end = .); |
| 224 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 225 | . = ALIGN(4); |
| 226 | /* finit data */ |
| 227 | PROVIDE_HIDDEN (__fini_array_start = .); |
| 228 | KEEP(*(SORT(.fini_array.*))) |
| 229 | KEEP(*(.fini_array)) |
| 230 | PROVIDE_HIDDEN (__fini_array_end = .); |
| 231 | |
| 232 | KEEP(*(.jcr*)) |
| 233 | . = ALIGN(4); |
| 234 | /* All data end */ |
| 235 | __data_end__ = .; |
| 236 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 237 | } > DTCM :rom_exec |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 238 | |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 239 | .sram.bss : |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 240 | { |
| 241 | . = ALIGN(16); |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 242 | #ifdef ETHOSU_FAST_MEMORY_SIZE |
Per Åstrand | 81e01af | 2021-02-19 13:45:26 +0100 | [diff] [blame] | 243 | *(.bss.ethosu_scratch); |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 244 | #else |
| 245 | *(.bss.tensor_arena) |
| 246 | #endif |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 247 | *.(output_data_sec) |
| 248 | } > SRAM :null |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 249 | |
| 250 | .ddr : |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 251 | { |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 252 | #ifdef ETHOSU_FAST_MEMORY_SIZE |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 253 | . = ALIGN(16); |
Jonny Svärd | f521be9 | 2021-03-01 14:35:49 +0100 | [diff] [blame] | 254 | *(.bss.tensor_arena) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 255 | #endif |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 256 | . = ALIGN(4); |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 257 | *(input_data_sec) |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 258 | . = ALIGN(16); |
| 259 | *(network_model_sec) |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 260 | *(expected_output_data_sec) |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 261 | } > DDR :rom_dram |
| 262 | |
| 263 | __eddr_data = ALIGN (16) ; |
| 264 | .sram.data : { |
| 265 | __sram_data_start__ = .; |
| 266 | *(.sram.data) |
| 267 | __sram_data_end__ = .; |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame^] | 268 | } > BRAM AT >DDR :rom_dram |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 269 | |
| 270 | .bss : |
| 271 | { |
| 272 | . = ALIGN(4); |
| 273 | __bss_start__ = .; |
| 274 | *(.bss) |
| 275 | *(.bss.*) |
| 276 | *(COMMON) |
| 277 | . = ALIGN(4); |
| 278 | __bss_end__ = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 279 | } > DTCM :null |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 280 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 281 | .heap (COPY) : |
| 282 | { |
| 283 | . = ALIGN(8); |
| 284 | __end__ = .; |
| 285 | PROVIDE(end = .); |
| 286 | . = . + __HEAP_SIZE; |
| 287 | . = ALIGN(8); |
| 288 | __HeapLimit = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 289 | } > DTCM :null |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 290 | |
| 291 | .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : |
| 292 | { |
| 293 | . = ALIGN(8); |
| 294 | __StackLimit = .; |
| 295 | . = . + __STACK_SIZE; |
| 296 | . = ALIGN(8); |
| 297 | __StackTop = .; |
Per Åstrand | 0b7bbb4 | 2021-03-25 12:34:24 +0100 | [diff] [blame] | 298 | } > DTCM :null |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 299 | PROVIDE(__stack = __StackTop); |
| 300 | |
| 301 | /* Check if data + heap + stack exceeds DTCM limit */ |
| 302 | ASSERT(__StackLimit >= __HeapLimit, "region DTCM overflowed with stack") |
| 303 | } |