Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /**************************************************************************** |
| 20 | * Includes |
| 21 | ****************************************************************************/ |
| 22 | |
| 23 | #include "target.hpp" |
| 24 | |
| 25 | #ifdef ETHOSU |
| 26 | #include <ethosu_driver.h> |
| 27 | #endif |
| 28 | |
| 29 | #include "uart.h" |
| 30 | |
| 31 | #include <stdio.h> |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 32 | #include <stdlib.h> |
| 33 | #include <inttypes.h> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 34 | |
| 35 | using namespace EthosU; |
| 36 | |
| 37 | /**************************************************************************** |
| 38 | * Defines |
| 39 | ****************************************************************************/ |
| 40 | |
| 41 | #define ETHOSU_BASE_ADDRESS 0x48102000 |
| 42 | |
| 43 | #define ETHOSU_IRQ 56 |
| 44 | |
| 45 | /**************************************************************************** |
| 46 | * Variables |
| 47 | ****************************************************************************/ |
| 48 | |
| 49 | #if defined(ETHOSU_FAST_MEMORY_SIZE) && ETHOSU_FAST_MEMORY_SIZE > 0 |
| 50 | __attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scratch[ETHOSU_FAST_MEMORY_SIZE]; |
| 51 | #else |
| 52 | #define ethosu_scratch 0 |
| 53 | #define ETHOSU_FAST_MEMORY_SIZE 0 |
| 54 | #endif |
| 55 | |
| 56 | /**************************************************************************** |
| 57 | * Cache maintenance |
| 58 | ****************************************************************************/ |
| 59 | |
| 60 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 61 | extern "C" { |
| 62 | void ethosu_flush_dcache(uint32_t *p, size_t bytes) { |
| 63 | if (p) |
| 64 | SCB_CleanDCache_by_Addr(p, bytes); |
| 65 | else |
| 66 | SCB_CleanDCache(); |
| 67 | } |
| 68 | |
| 69 | void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) { |
| 70 | if (p) |
| 71 | SCB_InvalidateDCache_by_Addr(p, bytes); |
| 72 | else |
| 73 | SCB_InvalidateDCache(); |
| 74 | } |
| 75 | } |
| 76 | #endif |
| 77 | |
| 78 | /**************************************************************************** |
| 79 | * Init |
| 80 | ****************************************************************************/ |
| 81 | |
| 82 | namespace { |
| 83 | |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 84 | extern "C" { |
| 85 | struct ExcContext { |
| 86 | uint32_t r0; |
| 87 | uint32_t r1; |
| 88 | uint32_t r2; |
| 89 | uint32_t r3; |
| 90 | uint32_t r12; |
| 91 | uint32_t lr; |
| 92 | uint32_t pc; |
| 93 | uint32_t xPsr; |
| 94 | }; |
| 95 | |
| 96 | void HardFault_Handler() { |
| 97 | int irq; |
| 98 | struct ExcContext *e; |
| 99 | uint32_t sp; |
| 100 | |
| 101 | asm volatile("mrs %0, ipsr \n" // Read IPSR (Exceptio number) |
| 102 | "sub %0, #16 \n" // Get it into IRQn_Type range |
| 103 | "tst lr, #4 \n" // Select the stack which was in use |
| 104 | "ite eq \n" |
| 105 | "mrseq %1, msp \n" |
| 106 | "mrsne %1, psp \n" |
| 107 | "mov %2, sp \n" |
| 108 | : "=r"(irq), "=r"(e), "=r"(sp)); |
| 109 | |
| 110 | printf("Hard fault. irq=%d, pc=0x%08" PRIx32 ", lr=0x%08" PRIx32 ", xpsr=0x%08" PRIx32 ", sp=0x%08" PRIx32 "\n", |
| 111 | irq, |
| 112 | e->pc, |
| 113 | e->lr, |
| 114 | e->xPsr, |
| 115 | sp); |
| 116 | printf( |
| 117 | "%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR); |
| 118 | exit(1); |
| 119 | } |
| 120 | } |
| 121 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 122 | #ifdef ETHOSU |
| 123 | void ethosuIrqHandler() { |
| 124 | ethosu_irq_handler(); |
| 125 | } |
| 126 | #endif |
| 127 | |
| 128 | } // namespace |
| 129 | |
| 130 | namespace EthosU { |
| 131 | |
| 132 | void targetSetup() { |
| 133 | // Initialize UART driver |
| 134 | uart_init(); |
| 135 | |
| 136 | #ifdef ETHOSU |
| 137 | // Initialize Ethos-U NPU driver |
| 138 | if (ethosu_init_v3(reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS), ethosu_scratch, ETHOSU_FAST_MEMORY_SIZE, 1, 1)) { |
| 139 | printf("Failed to initialize NPU.\n"); |
| 140 | return; |
| 141 | } |
| 142 | |
| 143 | /* Assumes SCB->VTOR point to RW memory */ |
| 144 | NVIC_SetVector(static_cast<IRQn_Type>(ETHOSU_IRQ), (uint32_t)ðosuIrqHandler); |
| 145 | NVIC_EnableIRQ(static_cast<IRQn_Type>(ETHOSU_IRQ)); |
| 146 | #endif |
| 147 | } |
| 148 | |
| 149 | } // namespace EthosU |