Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 1 | /* |
Davide Grohmann | 497ba58 | 2022-06-08 15:58:44 +0200 | [diff] [blame] | 2 | * Copyright (c) 2019-2022 Arm Limited. |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 19 | /* |
| 20 | * This is a simplified picture of the Corstone-300 memory system. |
| 21 | * Please refer to the Corstone SSE-300 Technical Reference Manual for |
| 22 | * further information. |
| 23 | * |
| 24 | * https://developer.arm.com/ip-products/subsystem/corstone/corstone-300 |
| 25 | * |
| 26 | * +---------------+ +---------------+ +------+ |
| 27 | * | Ethos-U55 | | Cortex-M55 +--+ ITCM | |
| 28 | * | | | | +------+ |
| 29 | * | | | | |
| 30 | * | | | | +------+ |
| 31 | * | M1 M0 | | +--+ DTCM | |
| 32 | * +---+-------+---+ +-------+-------+ +------+ |
| 33 | * | | | |
| 34 | * | +---+---------------+-----+ |
| 35 | * | | AMBA AXI NIC-400-Lite | |
| 36 | * | +---+-----------------+---+ |
| 37 | * | | | |
| 38 | * +---+-------+------------+ +--+-------+ |
| 39 | * | AMBA AXI NIC-400 | | SSE-300 | |
| 40 | * +---+--------+--------+--+ | SRAM | |
| 41 | * | | | +----------+ |
| 42 | * +---+---+ +--+---+ +--+--+ |
| 43 | * | Flash | | BRAM | | DDR | |
| 44 | * +-------+ +------+ +-----+ |
| 45 | * |
| 46 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 47 | * | Memory region name | Base addr | Size |IDAU| MCC load address + remarks | |
| 48 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 49 | * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | |
| 50 | * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | |
Nir Ekhauz | 1a96939 | 2021-10-21 15:42:22 +0300 | [diff] [blame] | 51 | * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0010_0000 | NS | 0x0100_0000; 1 MiB | |
| 52 | * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0010_0000 | S | Secure alias for NS BRAM | |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 53 | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | |
| 54 | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame] | 55 | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency) | |
| 56 | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S | Secure alias for NS internal SRAM | |
Nir Ekhauz | 1a96939 | 2021-10-21 15:42:22 +0300 | [diff] [blame] | 57 | * | QSPI external flash | 0x2800_0000 | 0x0080_0000 | NS | 8MB | |
| 58 | * | QSPI external flash | 0x3800_0000 | 0x0080_0000 | S | 8MB | |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 59 | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | |
| 60 | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | |
| 61 | * +-----------------------+-------------+-------------+----+--------------------------------------+ |
| 62 | * |
| 63 | * Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and |
| 64 | * the model should only be placed in those regions. |
| 65 | * |
| 66 | * Note: Alias regions means that secure and non-secure addresses are mapped to the same physical |
| 67 | * memory banks. |
| 68 | */ |
| 69 | |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 70 | #ifndef ETHOSU_MODEL |
| 71 | /* default value - '1', for DRAM */ |
| 72 | #define ETHOSU_MODEL 1 |
| 73 | #endif |
| 74 | |
| 75 | #ifndef ETHOSU_ARENA |
| 76 | /* default value - '1', for DRAM */ |
| 77 | #define ETHOSU_ARENA 1 |
| 78 | #endif |
| 79 | |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 80 | #ifndef STACK_SIZE |
| 81 | #define STACK_SIZE 0x8000 |
| 82 | #endif |
| 83 | |
| 84 | #ifndef HEAP_SIZE |
Kristofer Jonsson | 99f1942 | 2021-07-01 22:15:02 +0200 | [diff] [blame] | 85 | #define HEAP_SIZE 0x10000 |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 86 | #endif |
| 87 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 88 | #if defined(TRUSTZONE_BUILD) && !defined(ETHOSU_TEST) |
| 89 | /* |
| 90 | * Include trustzone.h with common addresses and sizes. |
| 91 | * The build configuration sets whether TRUSTZONE_SECURE is set or |
| 92 | * TRUSTZONE_NONSECURE which sets the memory start addresses and sizes. |
| 93 | */ |
| 94 | |
| 95 | #include "trustzone.h" |
| 96 | #define USE_TRUSTZONE |
| 97 | |
| 98 | #else //TRUSTZONE_BUILD |
| 99 | |
| 100 | #define LR_START 0x10000000 |
Per Åstrand | 79929ff | 2021-01-26 14:42:43 +0100 | [diff] [blame] | 101 | #define LR_SIZE 0x00080000 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 102 | |
| 103 | #define ITCM_START 0x10000000 |
| 104 | #define ITCM_SIZE 0x00080000 |
| 105 | |
| 106 | #define BRAM_START 0x11000000 |
Nir Ekhauz | 1a96939 | 2021-10-21 15:42:22 +0300 | [diff] [blame] | 107 | #define BRAM_SIZE 0x00100000 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 108 | |
| 109 | #define DTCM_START 0x30000000 |
| 110 | #define DTCM_SIZE 0x00080000 |
| 111 | |
| 112 | #define SRAM_START 0x31000000 |
| 113 | #define SRAM_SIZE 0x00200000 |
| 114 | |
Nir Ekhauz | 1a96939 | 2021-10-21 15:42:22 +0300 | [diff] [blame] | 115 | #define QSPI_START 0x38000000 |
| 116 | #define QSPI_SIZE 0x00800000 |
| 117 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 118 | #define DDR_START 0x70000000 |
| 119 | #define DDR_SIZE 0x02000000 |
| 120 | |
| 121 | #define STACK_HEAP 0x30080000 |
| 122 | |
| 123 | #endif //TRUSTZONE_BUILD |
| 124 | |
| 125 | /* ---------------------------------------------------------------------------- |
| 126 | Stack seal size definition |
| 127 | *----------------------------------------------------------------------------*/ |
| 128 | #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) |
| 129 | #define __STACKSEAL_SIZE ( 8 ) |
| 130 | #else |
| 131 | #define __STACKSEAL_SIZE ( 0 ) |
| 132 | #endif |
| 133 | |
| 134 | APP_IMAGE LR_START LR_SIZE |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 135 | { |
| 136 | ; ITCM 512kB |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 137 | rom_exec ITCM_START ITCM_SIZE |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 138 | { |
| 139 | *.o (RESET, +First) |
Kristofer Jonsson | ee3c613 | 2022-09-29 10:34:56 +0200 | [diff] [blame] | 140 | * (InRoot$$Sections, .init_array*, .ARM*) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 141 | ; Make sure reset_handler ends up in root segment, when split across |
| 142 | ; ITCM and DTCM |
| 143 | startup_ARMCM55.o |
Kristofer Jonsson | ee3c613 | 2022-09-29 10:34:56 +0200 | [diff] [blame] | 144 | .ANY2 (+RO) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 145 | } |
| 146 | |
Davide Grohmann | f4379e9 | 2022-06-15 11:20:41 +0200 | [diff] [blame] | 147 | ; DTCM 512kB |
| 148 | ; Only accessible from the Cortex-M |
| 149 | DTCM DTCM_START (DTCM_SIZE - STACK_SIZE - HEAP_SIZE - __STACKSEAL_SIZE) |
| 150 | { |
| 151 | .ANY1 (+RW +ZI) |
| 152 | } |
| 153 | |
| 154 | ARM_LIB_HEAP (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE - HEAP_SIZE) EMPTY ALIGN 8 HEAP_SIZE {} |
| 155 | ARM_LIB_STACK (STACK_HEAP - STACK_SIZE - __STACKSEAL_SIZE) EMPTY ALIGN 8 STACK_SIZE {} |
| 156 | |
| 157 | #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) |
| 158 | STACKSEAL +0 EMPTY __STACKSEAL_SIZE { |
| 159 | ; Reserve empty region for stack seal immediately after stack |
| 160 | } |
| 161 | #endif |
| 162 | } |
| 163 | |
| 164 | LOAD_REGION_BRAM BRAM_START BRAM_SIZE |
| 165 | { |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 166 | #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_SECURE) |
| 167 | ; MPS3 BRAM |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 168 | ; Shared between Cortex-M and the NPU |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 169 | BRAM BRAM_START (BRAM_SIZE - TZ_NSC_SIZE) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 170 | { |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 171 | * (.sram.data) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | ROM_NSC TZ_NSC_START TZ_NSC_SIZE |
| 175 | { |
| 176 | *(Veneer$$CMSE) |
| 177 | } |
| 178 | #else |
| 179 | ; MPS3 BRAM |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 180 | BRAM BRAM_START BRAM_SIZE |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 181 | { |
Kristofer Jonsson | b5f7cfe | 2021-03-10 17:13:52 +0100 | [diff] [blame] | 182 | * (.sram.data) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 183 | } |
| 184 | #endif |
Kristofer Jonsson | 34b1bd2 | 2022-09-19 14:14:39 +0200 | [diff] [blame] | 185 | |
Kristofer Jonsson | ee3c613 | 2022-09-29 10:34:56 +0200 | [diff] [blame] | 186 | TEXT1 +0 |
Kristofer Jonsson | 34b1bd2 | 2022-09-19 14:14:39 +0200 | [diff] [blame] | 187 | { |
Kristofer Jonsson | ee3c613 | 2022-09-29 10:34:56 +0200 | [diff] [blame] | 188 | ; Code segment is placed with higher priority (.ANY2) in ITCM. If ITCM gets |
| 189 | ; full, then the remaining symbols may be placed here in BRAM. |
| 190 | .ANY1 (+RO) |
Kristofer Jonsson | 34b1bd2 | 2022-09-19 14:14:39 +0200 | [diff] [blame] | 191 | } |
Davide Grohmann | f4379e9 | 2022-06-15 11:20:41 +0200 | [diff] [blame] | 192 | } |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 193 | |
Davide Grohmann | f4379e9 | 2022-06-15 11:20:41 +0200 | [diff] [blame] | 194 | LOAD_REGION_SRAM SRAM_START SRAM_SIZE |
| 195 | { |
Nir Ekhauz | 3adfbc1 | 2021-05-24 13:16:52 +0300 | [diff] [blame] | 196 | ; 2MB SSE-300 SRAM (3 cycles read latency) from M55/U55 |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 197 | SRAM SRAM_START SRAM_SIZE |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 198 | { |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 199 | #if (ETHOSU_MODEL == 0) |
| 200 | ; Place network model in SRAM |
| 201 | * (network_model_sec) |
| 202 | #endif |
| 203 | |
| 204 | #if (ETHOSU_ARENA == 0) |
| 205 | ; Place tensor arena in SRAM |
Jonny Svärd | f521be9 | 2021-03-01 14:35:49 +0100 | [diff] [blame] | 206 | * (.bss.tensor_arena) |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 207 | #endif |
| 208 | |
| 209 | ; Place scratch buffer in SRAM |
| 210 | * (.bss.ethosu_scratch) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 211 | } |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 212 | } |
| 213 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 214 | LOAD_REGION_1 DDR_START DDR_SIZE |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 215 | { |
| 216 | ; 2GB DDR4 available |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 217 | rom_dram DDR_START |
| 218 | #if defined(USE_TRUSTZONE) && defined(TRUSTZONE_NONSECURE) |
| 219 | { |
| 220 | } |
| 221 | #else //trustzone secure or non-trustzone |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 222 | ; Place model and its affiliates in DRAM |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 223 | { |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 224 | #if (ETHOSU_MODEL == 1) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 225 | * (network_model_sec) |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 226 | #endif |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 227 | * (input_data_sec) |
| 228 | * (expected_output_data_sec) |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 229 | * (output_data_sec) |
Davide Grohmann | 497ba58 | 2022-06-08 15:58:44 +0200 | [diff] [blame] | 230 | * (sec_command_stream, sec_weight_data, sec_input_data) |
Davide Grohmann | f4379e9 | 2022-06-15 11:20:41 +0200 | [diff] [blame] | 231 | |
| 232 | * (ethosu_core_in_queue) |
| 233 | * (ethosu_core_out_queue) |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 234 | } |
| 235 | |
Nir Ekhauz | 3c505ca | 2021-06-06 14:57:50 +0300 | [diff] [blame] | 236 | #if (ETHOSU_ARENA == 1) |
| 237 | ; Place tensor arena in DRAM if we have a fast memory area |
| 238 | ARENA +0 UNINIT ALIGN 16 |
| 239 | { |
| 240 | * (.bss.tensor_arena) |
| 241 | } |
| 242 | #endif |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 243 | #endif |
Kristofer Jonsson | 43ce491 | 2020-11-20 09:42:53 +0100 | [diff] [blame] | 244 | } |