blob: fab90cfa2ffbfced0e66f948fb90cfcf25be19a3 [file] [log] [blame]
Per Åstrand9f36f2e2021-09-30 09:57:34 +02001/*
2 * Copyright (c) 2021 Arm Limited. All rights reserved.
3 *
4 * This program is free software and is provided to you under the terms of the
5 * GNU General Public License version 2 as published by the Free Software
6 * Foundation, and any use by you of this program is subject to the terms
7 * of such GNU licence.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, you can access it online at
16 * http://www.gnu.org/licenses/gpl-2.0.html.
17 *
18 * SPDX-License-Identifier: GPL-2.0-only
19 */
20
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/reset-controller.h>
28
29#define JUNO_FPGA_RESET_DRIVER_VERSION "0.0.1"
30
31struct juno_fpga_reset {
32 struct reset_controller_dev rst;
33 struct device *dev;
34 void __iomem *base;
35};
36
37#define JUNO_FPGA_RESET_ID(base) (base)
38#define JUNO_FPGA_RESET_SOFT_RESET(base) ((base) + 0x140)
39#define JUNO_FPGA_RESET_CPU_WAIT(base) ((base) + 0x144)
40
41#define JUNO_FPGA_RESET_SET_RESET (0x1)
42#define JUNO_FPGA_RESET_UNSET_RESET (0x0)
43#define JUNO_FPGA_RESET_SET_CPUWAIT (0x1)
44#define JUNO_FPGA_RESET_UNSET_CPUWAIT (0x0)
45
46static void __iomem *verify_and_remap(struct device *dev,
47 struct resource *res)
48{
49 void __iomem *base = devm_ioremap_resource(dev, res);
50 u32 id;
51
52 if (IS_ERR(base))
53 return base;
54
55 id = readl(JUNO_FPGA_RESET_ID(base));
56
57 if (id != 0x2010f &&
58 id != 0x20110 &&
Per Åstrand049c59b2021-11-02 15:23:18 +010059 id != 0x20111 &&
60 id != 0x20112) {
61 dev_err(dev, "ID not matching");
Per Åstrand9f36f2e2021-09-30 09:57:34 +020062 return IOMEM_ERR_PTR(-EINVAL);
63 }
64
65 return base;
66}
67
68int juno_fpga_reset_assert(struct reset_controller_dev *rcdev,
69 unsigned long id)
70{
71 struct juno_fpga_reset *reset = container_of(rcdev, struct juno_fpga_reset,
72 rst);
73
74 /* pull reset */
75 dev_dbg(reset->dev, "Asserting reset");
76
77 /* set wait and reset */
78 writel(JUNO_FPGA_RESET_SET_RESET,
79 JUNO_FPGA_RESET_SOFT_RESET(reset->base));
80 writel(JUNO_FPGA_RESET_SET_CPUWAIT,
81 JUNO_FPGA_RESET_CPU_WAIT(reset->base));
82
83 writel(JUNO_FPGA_RESET_UNSET_RESET,
84 JUNO_FPGA_RESET_SOFT_RESET(reset->base));
85 return 0;
86}
87
88int juno_fpga_reset_deassert(struct reset_controller_dev *rcdev,
89 unsigned long id)
90{
91 struct juno_fpga_reset *reset = container_of(rcdev, struct juno_fpga_reset,
92 rst);
93
94 /* release wait */
95 dev_dbg(reset->dev, "Deasserting reset");
96
97 writel(JUNO_FPGA_RESET_UNSET_CPUWAIT,
98 JUNO_FPGA_RESET_CPU_WAIT(reset->base));
99 return 0;
100}
101
102static struct reset_control_ops juno_fpga_reset_ops = {
103 .assert = juno_fpga_reset_assert,
104 .deassert = juno_fpga_reset_deassert,
105};
106
107static const struct of_device_id juno_fpga_reset_match[] = {
108 { .compatible = "arm,mali_fpga_sysctl", .data = 0 },
109 { /* sentinel */ },
110};
111
112static int juno_fpga_reset_probe(struct platform_device *pdev)
113{
114 struct device *dev = &pdev->dev;
115 struct juno_fpga_reset *reset;
116 struct resource *res;
117
118 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
119 if (!reset)
120 return -ENOMEM;
121
122 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
123
124 reset->base = verify_and_remap(dev, res);
125 reset->dev = dev;
126
Per Åstrand049c59b2021-11-02 15:23:18 +0100127 if (IS_ERR(reset->base)) {
128 dev_err(dev, "Failed to verify and remap base address (%ld)", PTR_ERR(reset->base));
Per Åstrand9f36f2e2021-09-30 09:57:34 +0200129 return PTR_ERR(reset->base);
Per Åstrand049c59b2021-11-02 15:23:18 +0100130 }
Per Åstrand9f36f2e2021-09-30 09:57:34 +0200131
132 platform_set_drvdata(pdev, reset);
133
134 reset->rst.owner = THIS_MODULE;
135 reset->rst.nr_resets = 1;
136 reset->rst.ops = &juno_fpga_reset_ops;
137 reset->rst.of_node = pdev->dev.of_node;
138
Per Åstrand049c59b2021-11-02 15:23:18 +0100139 dev_info(dev, "registering to reset controller core");
Per Åstrand9f36f2e2021-09-30 09:57:34 +0200140
141 return devm_reset_controller_register(dev, &reset->rst);
142}
143
144static int juno_fpga_reset_remove(struct platform_device *pdev)
145{
146 return 0;
147}
148
149static struct platform_driver juno_fpga_reset_driver = {
150 .probe = juno_fpga_reset_probe,
151 .remove = juno_fpga_reset_remove,
152 .driver = {
153 .name = "juno-fpga-reset",
154 .of_match_table = of_match_ptr(juno_fpga_reset_match),
155 },
156};
157
158module_platform_driver(juno_fpga_reset_driver);
159
160MODULE_LICENSE("GPL v2");
161MODULE_AUTHOR("Arm Ltd");
162MODULE_DESCRIPTION("Arm Juno FPGA Reset Driver");
163MODULE_VERSION(JUNO_FPGA_RESET_DRIVER_VERSION);