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Tim Hall79d07d22020-04-27 18:20:16 +01001# Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved.
2#
3# SPDX-License-Identifier: Apache-2.0
4#
5# Licensed under the Apache License, Version 2.0 (the License); you may
6# not use this file except in compliance with the License.
7# You may obtain a copy of the License at
8#
9# www.apache.org/licenses/LICENSE-2.0
10#
11# Unless required by applicable law or agreed to in writing, software
12# distributed under the License is distributed on an AS IS BASIS, WITHOUT
13# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14# See the License for the specific language governing permissions and
15# limitations under the License.
Tim Hall79d07d22020-04-27 18:20:16 +010016# Description:
Tim Hallc8a73862020-10-27 12:43:14 +000017# Holds a container for Ethos-U and System architecture parameters.
Diego Russoea6111a2020-04-14 18:41:58 +010018import enum
Tim Hall79d07d22020-04-27 18:20:16 +010019from collections import namedtuple
20from configparser import ConfigParser
Diego Russoea6111a2020-04-14 18:41:58 +010021
Tim Hall79d07d22020-04-27 18:20:16 +010022import numpy as np
Diego Russoea6111a2020-04-14 18:41:58 +010023
Louis Verhaardaeae5672020-11-02 18:04:27 +010024from .api import NpuAccelerator
Tim Hall1bd531d2020-11-01 20:59:36 +000025from .errors import CliOptionError
26from .errors import ConfigOptionError
Dwight Lidmana9390f72020-05-13 12:00:08 +020027from .ethos_u55_regs.ethos_u55_regs import resampling_mode
Louis Verhaard69b31762020-11-17 09:45:20 +010028from .numeric_util import full_shape
Diego Russoe8a10452020-04-21 17:39:10 +010029from .numeric_util import round_up
30from .numeric_util import round_up_divide
Tim Hall4ed38bc2020-10-20 18:54:20 +010031from .operation import Kernel
Diego Russoea6111a2020-04-14 18:41:58 +010032from .operation import NpuBlockType
Tim Hall4ed38bc2020-10-20 18:54:20 +010033from .operation import PointXYZ
Diego Russoea6111a2020-04-14 18:41:58 +010034from .supported_operators import SupportedOperators
Diego Russoe8a10452020-04-21 17:39:10 +010035from .tensor import MemArea
Patrik Gustavssoneca2e952020-05-27 09:15:11 +020036from .tensor import MemType
Diego Russoe8a10452020-04-21 17:39:10 +010037from .tensor import TensorFormat
38from .tensor import TensorPurpose
Tim Hall79d07d22020-04-27 18:20:16 +010039
Tim Hall79d07d22020-04-27 18:20:16 +010040
41class Block:
42 def __init__(self, w, h, d):
43 self.width = w
44 self.height = h
45 self.depth = d
46
47 def __eq__(self, other):
48 if self.width == other.width and self.height == other.height and self.depth == other.depth:
49 return True
50 else:
51 return False
52
53 def __repr__(self):
54 return "<Block: {0},{1},{2}>".format(self.width, self.height, self.depth)
55
56 @classmethod
57 def from_string(cls, s):
58 w, h, c = (int(v) for v in s.split("x"))
59 return cls(w, h, c)
60
Louis Verhaard69b31762020-11-17 09:45:20 +010061 @classmethod
62 def from_shape(cls, shape) -> "Block":
63 """Converts the shape to a Block"""
64 shp = full_shape(3, shape, 1)
65 # Note: index from end, as len(shp) may be > 3
66 return Block(shp[-2], shp[-3], shp[-1])
67
Tim Hall79d07d22020-04-27 18:20:16 +010068
69class Rect:
70 def __init__(self, x, y, z, x2, y2, z2):
71 self.x = x
72 self.y = y
73 self.z = z
74 self.x2 = x2
75 self.y2 = y2
76 self.z2 = z2
77
78 def start(self):
79 return PointXYZ(self.x, self.y, self.z)
80
81 def end(self):
82 return PointXYZ(self.x2, self.y2, self.z2)
83
84 def size(self):
85 return Block(self.x2 - self.x + 1, self.y2 - self.y + 1, self.z2 - self.z + 1)
86
87 def __repr__(self):
88 return "<Rect: ({0},{1},{2}) ({3},{4},{5})>".format(self.x, self.y, self.z, self.x2, self.y2, self.z2)
89
90
Tim Hall79d07d22020-04-27 18:20:16 +010091class SHRAMElements:
92 IFM8 = 0
93 IFM16 = 1
94 IFM8_Elementwise = 2
95 IFM16_Elementwise = 3
Fredrik Svedberg597fd3f2020-08-13 10:02:53 +020096 IFM32 = 4
Fredrik Svedberga0c36242020-06-03 15:43:31 +020097 Acc16 = 5
98 Acc32 = 6
99 Acc40 = 7
Tim Hall79d07d22020-04-27 18:20:16 +0100100 Last = Acc40
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200101 BitSizes = np.array([8, 16, 8, 16, 32, 16, 32, 40], np.int32)
Louis Verhaardf98c6742020-05-12 14:22:38 +0200102 ByteSizes = BitSizes // 8
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200103 PostAlign = np.array([8, 8, 8, 8, 8, 1, 1, 1], np.int32)
104 PreAlign = np.array([1, 1, 1, 1, 1, 8, 8, 8], np.int32)
Tim Hall79d07d22020-04-27 18:20:16 +0100105
106
107class SHRAMBlockConfig:
108 def __init__(self, sizes, banks):
109 assert len(banks) == SHRAMElements.Last + 1
110 self.sizes = sizes
111 self.banks = banks
112
113
Tim Hallc8a73862020-10-27 12:43:14 +0000114# Area indices must match Ethos-U SHRAM layout spec
Tim Hall79d07d22020-04-27 18:20:16 +0100115class SharedBufferArea(enum.IntEnum):
116 OFM = 0
117 Weights = 1
118 IFM = 2
119 Accumulators = 3
120 Size = Accumulators + 1
121
122
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100123class Accelerator(enum.Enum):
124 Ethos_U55_32 = "ethos-u55-32"
125 Ethos_U55_64 = "ethos-u55-64"
126 Ethos_U55_128 = "ethos-u55-128"
127 Ethos_U55_256 = "ethos-u55-256"
Tim Hallc8a73862020-10-27 12:43:14 +0000128 Ethos_U65_256 = "ethos-u65-256"
129 Ethos_U65_512 = "ethos-u65-512"
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100130
131 @classmethod
132 def member_list(cls):
133 return [e.value for e in cls]
134
Louis Verhaardaeae5672020-11-02 18:04:27 +0100135 @classmethod
136 def from_npu_accelerator(cls, npu_accelerator: NpuAccelerator) -> "Accelerator":
137 """Converts the given public API object to Accelerator (used internally)"""
138 accelerator_map = {
139 NpuAccelerator.Ethos_U55_32: cls.Ethos_U55_32,
140 NpuAccelerator.Ethos_U55_64: cls.Ethos_U55_64,
141 NpuAccelerator.Ethos_U55_128: cls.Ethos_U55_128,
142 NpuAccelerator.Ethos_U55_256: cls.Ethos_U55_256,
143 NpuAccelerator.Ethos_U65_256: cls.Ethos_U65_256,
144 NpuAccelerator.Ethos_U65_512: cls.Ethos_U65_512,
145 }
146 assert npu_accelerator in accelerator_map, f"Unsupported accelerator {npu_accelerator}"
147 return accelerator_map[npu_accelerator]
148
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100149
Tim Hall1bd531d2020-11-01 20:59:36 +0000150@enum.unique
151class MemPort(enum.Enum):
152 Axi0 = enum.auto()
153 Axi1 = enum.auto()
154
155
Tim Hall79d07d22020-04-27 18:20:16 +0100156class ArchitectureFeatures:
Tim Hallc8a73862020-10-27 12:43:14 +0000157 """This class is a container for various parameters of the Ethos-U core
Diqing Zhonge8887a32020-09-24 09:53:48 +0200158 and system configuration that can be tuned, either by command line
Tim Hallc8a73862020-10-27 12:43:14 +0000159 parameters or by the Ethos-U architects. The class is often passed
Diqing Zhonge8887a32020-09-24 09:53:48 +0200160 around to passes that need to do architecture-dependent actions.
Tim Hall79d07d22020-04-27 18:20:16 +0100161
Diqing Zhonge8887a32020-09-24 09:53:48 +0200162 Note the difference between ArchitectureFeatures and CompilerOptions
Tim Hallc8a73862020-10-27 12:43:14 +0000163 - ArchitectureFeatures is for changing the Ethos-U and system architecture
Diqing Zhonge8887a32020-09-24 09:53:48 +0200164 - CompilerOptions is for changing the behaviour of the compiler
165 """
Tim Hall79d07d22020-04-27 18:20:16 +0100166
167 ArchitectureConfig = namedtuple(
168 "ArchitectureConfig", "macs cores ofm_ublock ifm_ublock shram_banks shram_granules elem_units"
169 )
170 accelerator_configs = {
Tim Hallc8a73862020-10-27 12:43:14 +0000171 Accelerator.Ethos_U65_512: ArchitectureConfig(
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200172 256, 2, Block(2, 2, 8), Block(2, 2, 8), 48, [8, 8, 8, 8, 16, 8, 16, 20], 8
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100173 ),
Tim Hallc8a73862020-10-27 12:43:14 +0000174 Accelerator.Ethos_U65_256: ArchitectureConfig(
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200175 256, 1, Block(2, 2, 8), Block(2, 2, 8), 48, [8, 8, 8, 8, 16, 8, 16, 20], 8
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100176 ),
177 Accelerator.Ethos_U55_256: ArchitectureConfig(
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200178 256, 1, Block(2, 2, 8), Block(2, 2, 8), 48, [8, 8, 8, 8, 16, 8, 16, 20], 8
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100179 ),
180 Accelerator.Ethos_U55_128: ArchitectureConfig(
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200181 128, 1, Block(2, 1, 8), Block(2, 2, 8), 24, [4, 4, 4, 4, 8, 4, 8, 12], 4
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100182 ),
183 Accelerator.Ethos_U55_64: ArchitectureConfig(
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200184 64, 1, Block(1, 1, 8), Block(1, 1, 8), 16, [2, 2, 2, 2, 4, 4, 4, 8], 2
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100185 ),
186 Accelerator.Ethos_U55_32: ArchitectureConfig(
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200187 32, 1, Block(1, 1, 4), Block(1, 1, 8), 16, [2, 2, 2, 2, 4, 4, 4, 4], 1
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100188 ),
Tim Hall79d07d22020-04-27 18:20:16 +0100189 }
190
191 OFMSplitDepth = 16
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100192 SubKernelMax = Block(8, 8, 65536)
Tim Hall79d07d22020-04-27 18:20:16 +0100193
Tim Hall1bd531d2020-11-01 20:59:36 +0000194 DEFAULT_CONFIG = "internal-default"
Louis Verhaard1e170182020-11-26 11:42:04 +0100195 MAX_BLOCKDEP = 3
Tim Hall1bd531d2020-11-01 20:59:36 +0000196
Tim Hall79d07d22020-04-27 18:20:16 +0100197 def __init__(
198 self,
Tim Hall1bd531d2020-11-01 20:59:36 +0000199 vela_config_files,
Tim Hall79d07d22020-04-27 18:20:16 +0100200 accelerator_config,
201 system_config,
Tim Hall1bd531d2020-11-01 20:59:36 +0000202 memory_mode,
Tim Hall79d07d22020-04-27 18:20:16 +0100203 override_block_config,
204 block_config_limit,
Tim Hall79d07d22020-04-27 18:20:16 +0100205 max_blockdep,
Patrik Gustavsson90831bc2020-08-24 16:26:11 +0200206 weight_estimation_scaling,
Tim Hall1bd531d2020-11-01 20:59:36 +0000207 verbose_config,
Tim Hall79d07d22020-04-27 18:20:16 +0100208 ):
209 accelerator_config = accelerator_config.lower()
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100210 if accelerator_config not in Accelerator.member_list():
Tim Hall1bd531d2020-11-01 20:59:36 +0000211 raise CliOptionError("--accelerator-config", self.accelerator_config, "Unknown accelerator configuration")
Manupa Karunaratned83d2e12020-07-20 12:05:32 +0100212 self.accelerator_config = Accelerator(accelerator_config)
Tim Hall79d07d22020-04-27 18:20:16 +0100213 accel_config = ArchitectureFeatures.accelerator_configs[self.accelerator_config]
214 self.config = accel_config
215
216 self.system_config = system_config
Tim Hall1bd531d2020-11-01 20:59:36 +0000217 self.memory_mode = memory_mode
Tim Hallc8a73862020-10-27 12:43:14 +0000218 self.is_ethos_u65_system = self.accelerator_config in (Accelerator.Ethos_U65_256, Accelerator.Ethos_U65_512)
Tim Hall79d07d22020-04-27 18:20:16 +0100219
Tim Hallc8a73862020-10-27 12:43:14 +0000220 self.max_outstanding_dma = 2 if self.is_ethos_u65_system else 1
Tim Hall289a41d2020-08-04 21:40:14 +0100221 self.max_outstanding_kernels = 3
222
Tim Hall79d07d22020-04-27 18:20:16 +0100223 self.ncores = accel_config.cores
224 self.ofm_ublock = accel_config.ofm_ublock
225 self.ifm_ublock = accel_config.ifm_ublock
Tim Hall79d07d22020-04-27 18:20:16 +0100226 self.ofm_block_max = Block(64, 32, 128)
227 self.override_block_config = override_block_config
228 self.block_config_limit = block_config_limit
229
Tim Hall79d07d22020-04-27 18:20:16 +0100230 self.max_blockdep = max_blockdep
Patrik Gustavsson90831bc2020-08-24 16:26:11 +0200231 self.weight_estimation_scaling = weight_estimation_scaling
Tim Hall79d07d22020-04-27 18:20:16 +0100232
233 dpu_min_height = accel_config.ofm_ublock.height
234 dpu_min_width = accel_config.ofm_ublock.width
235 dpu_dot_product_width = 8
236 dpu_min_ofm_channels = accel_config.ofm_ublock.depth
237
238 self.num_elem_wise_units = accel_config.elem_units
239 self.num_macs_per_cycle = dpu_min_height * dpu_min_width * dpu_dot_product_width * dpu_min_ofm_channels
240
Tim Hall1bd531d2020-11-01 20:59:36 +0000241 # Get system configuration and memory mode
242 self._get_vela_config(vela_config_files, verbose_config)
Tim Hall79d07d22020-04-27 18:20:16 +0100243
Tim Hall1bd531d2020-11-01 20:59:36 +0000244 self.axi_port_width = 128 if self.is_ethos_u65_system else 64
245 self.memory_bandwidths_per_cycle = self.axi_port_width * self.memory_clock_scales / 8
Tim Hall79d07d22020-04-27 18:20:16 +0100246
Tim Hall1bd531d2020-11-01 20:59:36 +0000247 self.memory_bandwidths_per_second = self.memory_bandwidths_per_cycle * self.core_clock
Tim Hall79d07d22020-04-27 18:20:16 +0100248
Diqing Zhonge8887a32020-09-24 09:53:48 +0200249 # Get output/activation performance numbers
250 self._generate_output_perf_tables(self.accelerator_config)
251
Tim Hall79d07d22020-04-27 18:20:16 +0100252 # sizes as N x H x W x C. we need to round up to these when allocating storage
253 self.storage_rounding_quantums = {
254 TensorFormat.Unknown: (1, 1, 1, 1),
255 TensorFormat.WeightsCompressed: (1, 1, 1, 1),
256 TensorFormat.NHWC: (1, 1, 1, 1),
257 TensorFormat.NHCWB16: (1, 1, 1, 16),
258 }
259
260 # brick sizes as N x H x W x C. We have to fetch whole bricks at a time
261 self.brick_sizes = {
262 TensorFormat.Unknown: (1, 1, 1, 1),
263 TensorFormat.WeightsCompressed: (1, 1, 1, 1),
264 TensorFormat.NHWC: (1, 1, 1, 1),
265 TensorFormat.NHCWB16: (1, 1, 1, 16),
266 }
267
Tim Hall79d07d22020-04-27 18:20:16 +0100268 self.default_weight_format = TensorFormat.WeightsCompressed
269 self.default_feature_map_format = TensorFormat.NHWC
270
Tim Hall79d07d22020-04-27 18:20:16 +0100271 self.tensor_storage_mem_area = {
272 # permanent mem_area
Tim Hall465582c2020-05-26 09:33:14 +0100273 TensorPurpose.Unknown: MemArea.Unknown,
Tim Hall79d07d22020-04-27 18:20:16 +0100274 TensorPurpose.Weights: self.permanent_storage_mem_area,
275 TensorPurpose.FeatureMap: self.feature_map_storage_mem_area,
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200276 TensorPurpose.LUT: self.permanent_storage_mem_area,
Tim Hall79d07d22020-04-27 18:20:16 +0100277 }
278
Patrik Gustavssoneca2e952020-05-27 09:15:11 +0200279 self.tensor_storage_mem_type = {
Dwight Lidman1a9d20e2020-08-11 12:10:36 +0200280 TensorPurpose.Unknown: MemType.Unknown,
Patrik Gustavssoneca2e952020-05-27 09:15:11 +0200281 TensorPurpose.Weights: MemType.Permanent_NPU,
282 TensorPurpose.FeatureMap: MemType.Scratch,
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200283 TensorPurpose.LUT: MemType.Scratch,
Patrik Gustavssoneca2e952020-05-27 09:15:11 +0200284 }
Tim Hall79d07d22020-04-27 18:20:16 +0100285
286 self.min_block_sizes = {
287 NpuBlockType.Default: (dpu_min_height, dpu_min_width),
288 NpuBlockType.VectorProduct: (1, 1),
289 NpuBlockType.ConvolutionMxN: (dpu_min_height, dpu_min_width),
290 NpuBlockType.Pooling: (dpu_min_height, dpu_min_width),
291 NpuBlockType.ConvolutionDepthWise: (dpu_min_height, dpu_min_width),
292 NpuBlockType.ElementWise: (1, 1),
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200293 NpuBlockType.ReduceSum: (dpu_min_height, dpu_min_width),
Tim Hall79d07d22020-04-27 18:20:16 +0100294 }
295
296 self.sub_kernel_limits = {
297 NpuBlockType.Default: (8, 8),
298 NpuBlockType.VectorProduct: (1, 1),
299 NpuBlockType.ConvolutionMxN: (8, 8),
300 NpuBlockType.Pooling: (8, 8),
301 NpuBlockType.ConvolutionDepthWise: (8, 8),
302 NpuBlockType.ElementWise: (1, 1),
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200303 NpuBlockType.ReduceSum: (8, 8),
Tim Hall79d07d22020-04-27 18:20:16 +0100304 }
305
306 # weights for scheduler search
307 from .npu_performance import make_bandwidth_array
308
309 self.bandwidth_weights = make_bandwidth_array()
310 self.bandwidth_weights[MemArea.Sram] = 1.0
311 self.bandwidth_weights[MemArea.Dram] = 10.0
312 self.bandwidth_weights[MemArea.OnChipFlash] = 2.0
313 self.bandwidth_weights[MemArea.OffChipFlash] = 20.0
314 self.cycles_weight = 40
315 self.max_sram_used_weight = 1000
316
Tim Hall1bd531d2020-11-01 20:59:36 +0000317 if self.is_spilling_enabled():
Patrik Gustavsson3ab94522020-06-29 17:36:55 +0200318 self.max_sram_used_weight = 0
Tim Hall79d07d22020-04-27 18:20:16 +0100319
320 # Shared Buffer Block allocations
321 self.shram_bank_size = 1024 # bytes
322 self.shram_size_bytes = accel_config.shram_banks * self.shram_bank_size
323 self.shram_reserved_output_banks = 2
324 self.shram_reserved_weight_banks = 0
325 self.shram_reserved_unused_banks = 2 if accel_config.shram_banks > 16 else 0
326 self.shram_total_banks = accel_config.shram_banks - self.shram_reserved_unused_banks
327 self.shram_bank_granules = np.array(accel_config.shram_granules, np.int32)
Louis Verhaard0b8268a2020-08-05 16:11:29 +0200328 self.shram_lut_size = 2048
329 # SHRAM base address of the activation lookup table
330 self.shram_lut_address = self.shram_bank_size * self.available_shram_banks(True)
Tim Hall79d07d22020-04-27 18:20:16 +0100331
332 # Build a map of acceptable IFM/OFM block configurations up to the maximum
333 # IFM/OFM block size.
334 ifm_block_max = self.get_ifm_block_size(32, self.ofm_block_max, Kernel(8, 8))
335 self.block_config_map = dict()
336 self.generate_block_config_map(Block(ifm_block_max.width, ifm_block_max.height, 128))
337
338 # Setup supported operators and restriction checkers class
Fredrik Svedberg880e7352020-08-25 11:31:47 +0200339 self.supported_operators = SupportedOperators()
Tim Hall79d07d22020-04-27 18:20:16 +0100340
Louis Verhaard0b8268a2020-08-05 16:11:29 +0200341 # Returns available number of SHRAM banks depending on activation lookup table
342 # being used or not
343 def available_shram_banks(self, uses_activation_lut):
344 banks = self.shram_total_banks
345 if uses_activation_lut and self.shram_reserved_unused_banks == 0:
346 banks -= 2
347 return banks
348
Tim Hall79d07d22020-04-27 18:20:16 +0100349 # Calculate block configuration for ALL known IFM operations and
350 # accumulator sizes. Consumers will need to select their preferred
351 # operation and bit-width at read-time.
352 def generate_block_config(self, width, height, depth):
Louis Verhaardf98c6742020-05-12 14:22:38 +0200353 # Number of bytes required for any SHRAM element for a FM of given dimensions.
354 # For IFM: size = H*W*Align(D*BYTE_WIDTH, 8)
355 # For ACC: size = H*W*Align(D,8)*BYTE_WIDTH
356 d1 = round_up(depth, SHRAMElements.PreAlign)
357 d2 = round_up(d1 * SHRAMElements.ByteSizes, SHRAMElements.PostAlign)
358 size_bytes = (height * width) * d2
359
Tim Hall79d07d22020-04-27 18:20:16 +0100360 # Convert byte size (rounded) to size in banks
361 size_banks = round_up_divide(size_bytes, self.shram_bank_size)
362 size_banks *= 2 # Double buffer the IFM/Acc (need twice as many banks)
363 # Round bank requirement to bank granularity
364 required_banks = round_up(size_banks, self.shram_bank_granules)
365 return SHRAMBlockConfig(size_bytes, required_banks)
366
367 @staticmethod
368 def make_block_config_key(width, height, depth):
369 return (int(height), int(width), int(depth))
370
371 def get_block_config(self, width, height, depth):
372 assert depth <= self.ofm_block_max.depth
373 key = ArchitectureFeatures.make_block_config_key(width, height, depth)
374 config = self.block_config_map.get(key, None)
375 return config
376
377 # Generate a key:value map of possible block configurations, where the
378 # key is compounded from the block dimensions: 0x00HHWWCC
379 def generate_block_config_map(self, block: Block):
380 for h in range(1, block.height + 1):
381 for w in range(1, block.width + 1):
382 # All possible IFM/OFM depth values
383 for c in [4, 8, 12, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128]:
384 key = ArchitectureFeatures.make_block_config_key(w, h, c)
385 self.block_config_map[key] = self.generate_block_config(w, h, c)
386
Diqing Zhonge8887a32020-09-24 09:53:48 +0200387 def _generate_output_perf_tables(self, accel_config):
388 if accel_config == Accelerator.Ethos_U55_32:
389 self.output_cycles_per_elem = (2.0, 3.0, 3.0, 3.0, 4.0, 6.0, 1.0, 2.0)
390 self.activation_cycles_per_elem = (1.0, 1.0, 0.0)
391 elif accel_config == Accelerator.Ethos_U55_64:
392 self.output_cycles_per_elem = (1.0, 1.5, 1.5, 1.5, 2.0, 3.0, 0.5, 1.0)
393 self.activation_cycles_per_elem = (1.0, 1.0, 0.0)
394 elif accel_config == Accelerator.Ethos_U55_128:
395 self.output_cycles_per_elem = (0.75, 1.25, 0.75, 0.75, 1.0, 1.5, 0.25, 0.5)
396 self.activation_cycles_per_elem = (1.0, 0.5, 0.0)
Tim Hallc8a73862020-10-27 12:43:14 +0000397 elif accel_config in (Accelerator.Ethos_U55_256, Accelerator.Ethos_U65_256):
Diqing Zhonge8887a32020-09-24 09:53:48 +0200398 self.output_cycles_per_elem = (0.625, 1.125, 0.5, 0.375, 0.5, 0.75, 0.125, 0.25)
399 self.activation_cycles_per_elem = (1.0, 0.25, 0.0)
400 else:
Tim Hallc8a73862020-10-27 12:43:14 +0000401 assert accel_config == Accelerator.Ethos_U65_512
Diqing Zhonge8887a32020-09-24 09:53:48 +0200402 self.output_cycles_per_elem = (0.3125, 0.5625, 0.25, 0.1875, 0.25, 0.375, 0.0625, 0.125)
403 self.activation_cycles_per_elem = (0.5, 0.125, 0.0)
404
Tim Hall79d07d22020-04-27 18:20:16 +0100405 def calc_ifm_block_depth(self, ifm_depth, ifm_bits):
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200406 assert ifm_bits in (8, 16, 32)
Tim Hall79d07d22020-04-27 18:20:16 +0100407 assert ifm_depth > 0
408 ifm_depth = round_up(ifm_depth, self.ifm_ublock.depth)
Fredrik Svedberga0c36242020-06-03 15:43:31 +0200409 max_block_depth = 8 * 32 // ifm_bits
Tim Hall79d07d22020-04-27 18:20:16 +0100410 return min(max_block_depth, ifm_depth)
411
412 # Calculate the size of the IFM block given a depth, target OFM block and a kernel
Tim Hallc30f4952020-06-15 20:47:35 +0100413 def get_ifm_block_size(
414 self,
415 ifm_block_depth,
416 ofm_block: Block,
417 kernel: Kernel,
418 subkernel: Block = Block(8, 8, 65536),
419 ifm_resampling_mode=resampling_mode.NONE,
420 ):
Dwight Lidmana9390f72020-05-13 12:00:08 +0200421 upscaling = 1 if ifm_resampling_mode == resampling_mode.NONE else 2
Tim Hall79d07d22020-04-27 18:20:16 +0100422 # Height
423 ifm_odd_2x_height_enable = 0
424 dilated_kernel_height = ((kernel.height - 1) * kernel.dilation.y) + 1
425 ifm_block_height = (
426 (ofm_block.height - 1) * kernel.stride.y
427 + min(subkernel.height, dilated_kernel_height)
428 + ifm_odd_2x_height_enable
429 ) // upscaling
430
Dwight Lidman0538a772020-05-06 14:09:17 +0200431 ifm_block_height = round_up(ifm_block_height, self.ofm_ublock.height)
Tim Hall79d07d22020-04-27 18:20:16 +0100432
433 # Width
434 ifm_odd_2x_width_enable = 0
435 dilated_kernel_width = ((kernel.width - 1) * kernel.dilation.x) + 1
436 ifm_block_width = (
437 (ofm_block.width - 1) * kernel.stride.x
438 + min(subkernel.width, dilated_kernel_width)
439 + ifm_odd_2x_width_enable
440 ) // upscaling
441
Dwight Lidman0538a772020-05-06 14:09:17 +0200442 ifm_block_width = round_up(ifm_block_width, self.ofm_ublock.width)
Tim Hall79d07d22020-04-27 18:20:16 +0100443
444 return Block(ifm_block_width, ifm_block_height, ifm_block_depth)
445
Tim Hall1bd531d2020-11-01 20:59:36 +0000446 def is_spilling_enabled(self):
Tim Hall79d07d22020-04-27 18:20:16 +0100447 """
Tim Hall1bd531d2020-11-01 20:59:36 +0000448 Spilling is a feature that allows the Ethos-U to use a dedicated SRAM as a cache for various types of data
Tim Hall79d07d22020-04-27 18:20:16 +0100449 """
Tim Hall1bd531d2020-11-01 20:59:36 +0000450 return (
451 self._mem_port_mapping(self.cache_mem_area) == MemArea.Sram and self.cache_mem_area != self.arena_mem_area
452 )
Tim Hall79d07d22020-04-27 18:20:16 +0100453
Tim Hall1bd531d2020-11-01 20:59:36 +0000454 def _mem_port_mapping(self, mem_port):
455 mem_port_mapping = {MemPort.Axi0: self.axi0_port, MemPort.Axi1: self.axi1_port}
456 return mem_port_mapping[mem_port]
Tim Hall79d07d22020-04-27 18:20:16 +0100457
Tim Hall1bd531d2020-11-01 20:59:36 +0000458 def _set_default_sys_config(self):
Tim Hall1bd531d2020-11-01 20:59:36 +0000459 # ArchitectureFeatures.DEFAULT_CONFIG values
460 if self.is_ethos_u65_system:
461 # Default Ethos-U65 system configuration
462 # Ethos-U65 Client-Server: SRAM (16 GB/s) and DRAM (12 GB/s)
463 self.core_clock = 1e9
464 self.axi0_port = MemArea.Sram
465 self.axi1_port = MemArea.Dram
466 self.memory_clock_scales[MemArea.Sram] = 1.0
467 self.memory_clock_scales[MemArea.Dram] = 0.75 # 3 / 4
Tim Hall79d07d22020-04-27 18:20:16 +0100468 else:
Tim Hall1bd531d2020-11-01 20:59:36 +0000469 # Default Ethos-U55 system configuration
470 # Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s)
471 self.core_clock = 500e6
472 self.axi0_port = MemArea.Sram
473 self.axi1_port = MemArea.OffChipFlash
474 self.memory_clock_scales[MemArea.Sram] = 1.0
475 self.memory_clock_scales[MemArea.OffChipFlash] = 0.125 # 1 / 8
Tim Hall79d07d22020-04-27 18:20:16 +0100476
Tim Hall1bd531d2020-11-01 20:59:36 +0000477 def _set_default_mem_mode(self):
Tim Hall1bd531d2020-11-01 20:59:36 +0000478 # ArchitectureFeatures.DEFAULT_CONFIG values
479 if self.is_ethos_u65_system:
480 # Default Ethos-U65 memory mode
481 # Dedicated SRAM: SRAM is only used by the Ethos-U
482 self.const_mem_area = MemPort.Axi1
483 self.arena_mem_area = MemPort.Axi1
484 self.cache_mem_area = MemPort.Axi0
485 self.cache_sram_size = 384 * 1024
486 else:
487 # Default Ethos-U65 memory mode
488 self.const_mem_area = MemPort.Axi1
489 self.arena_mem_area = MemPort.Axi0
490 self.cache_mem_area = MemPort.Axi0
Tim Hall79d07d22020-04-27 18:20:16 +0100491
Tim Hall1bd531d2020-11-01 20:59:36 +0000492 def _get_vela_config(self, vela_config_files, verbose_config):
493 """
494 Gets the system configuration and memory modes from one or more Vela configuration file(s) or uses some
495 defaults.
496 """
Tim Hall79d07d22020-04-27 18:20:16 +0100497
Tim Hall1bd531d2020-11-01 20:59:36 +0000498 # all properties are optional and are initialised to a value of 1 (or the equivalent)
499 self.core_clock = 1
500 self.axi0_port = MemArea(1)
501 self.axi1_port = MemArea(1)
502 self.memory_clock_scales = np.ones(MemArea.Size)
503 self.const_mem_area = MemPort(1)
504 self.arena_mem_area = MemPort(1)
505 self.cache_mem_area = MemPort(1)
506 self.cache_sram_size = 1
Tim Hall79d07d22020-04-27 18:20:16 +0100507
Tim Hall1bd531d2020-11-01 20:59:36 +0000508 # read configuration file(s)
509 self.vela_config = None
510
511 if vela_config_files is not None:
512 self.vela_config = ConfigParser()
513 self.vela_config.read(vela_config_files)
514
515 # read system configuration
516 sys_cfg_section = "System_Config." + self.system_config
517
518 if self.vela_config is not None and self.vela_config.has_section(sys_cfg_section):
519 self.core_clock = float(self._read_config(sys_cfg_section, "core_clock", self.core_clock))
520 self.axi0_port = MemArea[self._read_config(sys_cfg_section, "axi0_port", self.axi0_port)]
521 self.axi1_port = MemArea[self._read_config(sys_cfg_section, "axi1_port", self.axi1_port)]
522
523 for mem_area in (self.axi0_port, self.axi1_port):
524 self.memory_clock_scales[mem_area] = float(
525 self._read_config(
526 sys_cfg_section, mem_area.name + "_clock_scale", self.memory_clock_scales[mem_area]
527 )
528 )
529
530 elif self.system_config == ArchitectureFeatures.DEFAULT_CONFIG:
531 self._set_default_sys_config()
532
533 elif vela_config_files is None:
Michael McGeagh7a6f8432020-12-02 15:29:22 +0000534 raise CliOptionError("--config", vela_config_files, "Vela config file not specified")
Tim Hall1bd531d2020-11-01 20:59:36 +0000535
536 else:
537 raise CliOptionError(
Michael McGeagh7a6f8432020-12-02 15:29:22 +0000538 "--system-config", self.system_config, f"Section {sys_cfg_section} not found in Vela config file",
Tim Hall79d07d22020-04-27 18:20:16 +0100539 )
Tim Hall79d07d22020-04-27 18:20:16 +0100540
Tim Hall1bd531d2020-11-01 20:59:36 +0000541 # read the memory mode
542 mem_mode_section = "Memory_Mode." + self.memory_mode
Tim Hall79d07d22020-04-27 18:20:16 +0100543
Tim Hall1bd531d2020-11-01 20:59:36 +0000544 if self.vela_config is not None and self.vela_config.has_section(mem_mode_section):
545 self.const_mem_area = MemPort[
546 self._read_config(mem_mode_section, "const_mem_area", self.const_mem_area.name)
547 ]
548 self.arena_mem_area = MemPort[
549 self._read_config(mem_mode_section, "arena_mem_area", self.arena_mem_area.name)
550 ]
551 self.cache_mem_area = MemPort[
552 self._read_config(mem_mode_section, "cache_mem_area", self.cache_mem_area.name)
553 ]
554 self.cache_sram_size = int(self._read_config(mem_mode_section, "cache_sram_size", self.cache_sram_size))
Patrik Gustavssoneca2e952020-05-27 09:15:11 +0200555
Tim Hall1bd531d2020-11-01 20:59:36 +0000556 elif self.memory_mode == ArchitectureFeatures.DEFAULT_CONFIG:
557 self._set_default_mem_mode()
Patrik Gustavsson5f47c052020-06-25 12:56:04 +0200558
Tim Hall1bd531d2020-11-01 20:59:36 +0000559 elif vela_config_files is None:
Michael McGeagh7a6f8432020-12-02 15:29:22 +0000560 raise CliOptionError("--config", vela_config_files, "Vela config file not specified")
Patrik Gustavssoneca2e952020-05-27 09:15:11 +0200561
Tim Hall1bd531d2020-11-01 20:59:36 +0000562 else:
563 raise CliOptionError(
Michael McGeagh7a6f8432020-12-02 15:29:22 +0000564 "--memory-mode", self.memory_mode, f"Section {mem_mode_section} not found in Vela config file",
Tim Hall1bd531d2020-11-01 20:59:36 +0000565 )
Tim Hall79d07d22020-04-27 18:20:16 +0100566
Tim Hall1bd531d2020-11-01 20:59:36 +0000567 # override sram to onchipflash
568 if self._mem_port_mapping(self.const_mem_area) == MemArea.Sram:
569 if self.const_mem_area == self.arena_mem_area == self.cache_mem_area:
570 print(
571 "Info: Changing const_mem_area from Sram to OnChipFlash. This will use the same characteristics as"
572 " Sram."
573 )
574 if self.const_mem_area == MemPort.Axi0:
575 self.const_mem_area = MemPort.Axi1
576 self.axi1_port = MemArea.OnChipFlash
577 else:
578 self.const_mem_area = MemPort.Axi0
579 self.axi0_port = MemArea.OnChipFlash
580 self.memory_clock_scales[MemArea.OnChipFlash] = self.memory_clock_scales[MemArea.Sram]
581
582 # check configuration
583 if self._mem_port_mapping(self.cache_mem_area) != MemArea.Sram:
584 raise ConfigOptionError("cache_mem_area", self._mem_port_mapping(self.cache_mem_area).name, "Sram")
585
586 if self.is_ethos_u65_system:
587 if self._mem_port_mapping(self.const_mem_area) not in (
588 MemArea.Dram,
589 MemArea.OnChipFlash,
590 MemArea.OffChipFlash,
591 ):
592 raise ConfigOptionError(
593 "const_mem_area",
594 self._mem_port_mapping(self.const_mem_area).name,
595 "Dram or OnChipFlash or OffChipFlash",
596 )
597
598 if self._mem_port_mapping(self.arena_mem_area) not in (MemArea.Sram, MemArea.Dram):
599 raise ConfigOptionError(
600 "arena_mem_area", self._mem_port_mapping(self.arena_mem_area).name, "Sram or Dram"
601 )
602 else:
603 if self._mem_port_mapping(self.const_mem_area) not in (MemArea.OnChipFlash, MemArea.OffChipFlash):
604 raise ConfigOptionError(
605 "const_mem_area", self._mem_port_mapping(self.const_mem_area).name, "OnChipFlash or OffChipFlash"
606 )
607
608 if self._mem_port_mapping(self.arena_mem_area) != MemArea.Sram:
609 raise ConfigOptionError("arena_mem_area", self._mem_port_mapping(self.arena_mem_area).name, "Sram")
610
611 # assign existing memory areas
612 self.permanent_storage_mem_area = self._mem_port_mapping(self.const_mem_area)
613 self.feature_map_storage_mem_area = self._mem_port_mapping(self.arena_mem_area)
614 self.fast_storage_mem_area = self._mem_port_mapping(self.cache_mem_area)
615
616 self.sram_size = self.cache_sram_size if self.is_spilling_enabled() else 9999 * 1024 * 1024
617
618 # display the system configuration and memory mode
619 if verbose_config:
620 print(f"System Configuration ({self.system_config}):")
621 print(f" core_clock = {self.core_clock}")
622 print(f" axi0_port = {self.axi0_port.name}")
623 print(f" axi1_port = {self.axi1_port.name}")
624 for mem in (MemArea.Sram, MemArea.Dram, MemArea.OnChipFlash, MemArea.OffChipFlash):
625 print(f" {mem.name}_clock_scales = {self.memory_clock_scales[mem]}")
626
627 print(f"Memory Mode ({self.memory_mode}):")
628 print(f" const_mem_area = {self.const_mem_area.name}")
629 print(f" arena_mem_area = {self.arena_mem_area.name}")
630 print(f" cache_mem_area = {self.cache_mem_area.name}")
631 print(f" cache_sram_size = {self.cache_sram_size}")
632
633 print("Architecture Settings:")
634 print(f" permanent_storage_mem_area = {self.permanent_storage_mem_area.name}")
635 print(f" feature_map_storage_mem_area = {self.feature_map_storage_mem_area.name}")
636 print(f" fast_storage_mem_area = {self.fast_storage_mem_area.name}")
637 print(f" sram_size = {self.sram_size}")
638
639 def _read_config(self, section, key, current_value):
Tim Hall79d07d22020-04-27 18:20:16 +0100640 """
Tim Hall1bd531d2020-11-01 20:59:36 +0000641 Reads a given key from a particular section in the Vela config file. If the section contains the 'inherit'
642 option then we recurse into the section specified. If inherited sections result in multiple keys for a
643 particular option then the key from the parent section is used, regardless of the parsing order
Tim Hall79d07d22020-04-27 18:20:16 +0100644 """
Tim Hall1bd531d2020-11-01 20:59:36 +0000645 if not self.vela_config.has_section(section):
Michael McGeagh7a6f8432020-12-02 15:29:22 +0000646 raise ConfigOptionError("section", f"{section}. The section was not found in the Vela config file(s)")
Tim Hall1bd531d2020-11-01 20:59:36 +0000647
648 result = str(current_value)
649 if self.vela_config.has_option(section, "inherit"):
650 inheritance_section = self.vela_config.get(section, "inherit")
651 # check for recursion loop
652 if inheritance_section == section:
653 raise ConfigOptionError(
Michael McGeagh7a6f8432020-12-02 15:29:22 +0000654 "inherit", f"{inheritance_section}. This references its own section and recursion is not allowed",
Tim Hall1bd531d2020-11-01 20:59:36 +0000655 )
656 result = self._read_config(inheritance_section, key, result)
657
658 if self.vela_config.has_option(section, key):
659 result = self.vela_config.get(section, key)
660
Tim Hall79d07d22020-04-27 18:20:16 +0100661 return result
Louis Verhaard52078302020-11-18 13:35:06 +0100662
663
Louis Verhaard061eeb42020-11-27 08:24:03 +0100664# Cache for default arch instances, as these are expensive to create
665default_arch_cache = dict()
666
667
Louis Verhaard52078302020-11-18 13:35:06 +0100668def create_default_arch(accelerator: Accelerator) -> ArchitectureFeatures:
669 """Creates architecture features object using default settings"""
Louis Verhaard061eeb42020-11-27 08:24:03 +0100670 if accelerator not in default_arch_cache:
671 default_arch_cache[accelerator] = ArchitectureFeatures(
672 vela_config_files=None,
673 accelerator_config=accelerator.value,
674 system_config=ArchitectureFeatures.DEFAULT_CONFIG,
675 memory_mode=ArchitectureFeatures.DEFAULT_CONFIG,
676 override_block_config=None,
677 block_config_limit=None,
678 max_blockdep=ArchitectureFeatures.MAX_BLOCKDEP,
679 weight_estimation_scaling=1.0,
680 verbose_config=False,
681 )
682 return default_arch_cache[accelerator]