Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1 | # Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. |
| 2 | # |
| 3 | # SPDX-License-Identifier: Apache-2.0 |
| 4 | # |
| 5 | # Licensed under the Apache License, Version 2.0 (the License); you may |
| 6 | # not use this file except in compliance with the License. |
| 7 | # You may obtain a copy of the License at |
| 8 | # |
| 9 | # www.apache.org/licenses/LICENSE-2.0 |
| 10 | # |
| 11 | # Unless required by applicable law or agreed to in writing, software |
| 12 | # distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 13 | # WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | # See the License for the specific language governing permissions and |
| 15 | # limitations under the License. |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 16 | # Description: |
| 17 | # Serialises and packs an NPU subgraph into tensors. |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 18 | import struct |
| 19 | |
| 20 | import numpy as np |
| 21 | |
| 22 | from . import driver_actions |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 23 | from .data_type import DataType |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 24 | from .nn_graph import PassPlacement |
| 25 | from .operation import Operation |
| 26 | from .tensor import MemArea |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 27 | from .tensor import MemType |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 28 | from .tensor import Tensor |
| 29 | from .tensor import TensorFormat |
| 30 | from .tensor import TensorPurpose |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 31 | |
| 32 | |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 33 | def make_memory_tensor(name, mem_area, mem_type, sz, want_values, arch): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 34 | tens = Tensor([sz], DataType.uint8, name) |
| 35 | tens.mem_area = mem_area |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 36 | tens.mem_type = mem_type |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 37 | tens.purpose = TensorPurpose.FeatureMap |
| 38 | tens.set_format(TensorFormat.NHWC, arch) |
| 39 | if want_values: |
| 40 | tens.values = np.zeros(tens.shape, np.uint8) |
| 41 | return tens |
| 42 | |
| 43 | |
| 44 | def copy_compressed_values_to_memory_tensor(memory_tensor, src_tensor): |
| 45 | start_addr = src_tensor.address |
| 46 | for compressed_values in src_tensor.compressed_values: |
| 47 | end_addr = start_addr + len(compressed_values) |
| 48 | memory_tensor.values[start_addr:end_addr] = compressed_values |
| 49 | start_addr = end_addr |
| 50 | |
Tim Hall | c30f495 | 2020-06-15 20:47:35 +0100 | [diff] [blame] | 51 | |
Charles Xu | 7879222 | 2020-05-13 10:15:26 +0200 | [diff] [blame] | 52 | def copy_ifm_values_to_memory_tensor(memory_tensor, src_tensor): |
| 53 | start_addr = src_tensor.address |
Charles Xu | 9a03fdf | 2020-07-02 15:12:40 +0200 | [diff] [blame] | 54 | values = src_tensor.quant_values.flatten() |
Fredrik Svedberg | bb1a92a | 2020-08-27 15:51:50 +0200 | [diff] [blame^] | 55 | if src_tensor.dtype.size_in_bytes() > 1: |
| 56 | values = np.frombuffer(values.tobytes(), dtype=np.uint8) |
Charles Xu | 9a03fdf | 2020-07-02 15:12:40 +0200 | [diff] [blame] | 57 | end_addr = start_addr + values.size |
| 58 | memory_tensor.values[start_addr:end_addr] = values |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 59 | |
Tim Hall | c30f495 | 2020-06-15 20:47:35 +0100 | [diff] [blame] | 60 | |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 61 | def serialise_npu_subgraph_into_tensors(nng, sg, arch, scratch_tens, scratch_fast_tens, flash_tens): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 62 | if sg.placement != PassPlacement.Npu: |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 63 | return scratch_tens, scratch_fast_tens, flash_tens |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 64 | |
| 65 | flash_area = arch.permanent_storage_mem_area |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 66 | scratch_area = arch.feature_map_storage_mem_area |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 67 | scratch_fast_area = arch.fast_storage_mem_area |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 68 | |
| 69 | flash_size = sg.memory_used.get(flash_area, 0) |
| 70 | scratch_size = sg.memory_used.get(scratch_area, 0) |
| 71 | |
| 72 | # Prepare driver actions for this command tensor |
| 73 | da_list = [] |
| 74 | driver_actions.emit_fourcc(da_list, "COP1") |
| 75 | driver_actions.emit_config(da_list, 0, 1, arch) |
| 76 | driver_actions.emit_cmd_stream_header(da_list, len(sg.register_command_stream)) |
| 77 | |
| 78 | # Append command stream words |
| 79 | da_list.extend(sg.register_command_stream) |
| 80 | |
| 81 | # Convert to bytes |
| 82 | payload_bytes = struct.pack("<{0}I".format(len(da_list)), *da_list) |
| 83 | |
| 84 | command_stream_size_bytes = len(payload_bytes) |
| 85 | |
| 86 | # Adjust the bits per element calculation to exclude metadata generated by Vela |
| 87 | nng.total_size[flash_area] = nng.total_size.get(flash_area, 0) - flash_size - command_stream_size_bytes |
| 88 | nng.total_elements[flash_area] = nng.total_elements.get(flash_area, 0) - flash_size - command_stream_size_bytes |
| 89 | nng.total_size[scratch_area] = nng.total_size.get(scratch_area, 0) - scratch_size |
| 90 | nng.total_elements[scratch_area] = nng.total_elements.get(scratch_area, 0) - scratch_size |
| 91 | |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 92 | if scratch_area != scratch_fast_area: |
| 93 | nng.total_size[scratch_fast_area] = nng.total_size.get(scratch_fast_area, 0) |
| 94 | nng.total_elements[scratch_fast_area] = nng.total_elements.get(scratch_fast_area, 0) |
| 95 | |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 96 | if flash_tens == scratch_tens is None: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 97 | # First Npu subgraph, create scratch and flash tensors |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 98 | sg.scratch_tensor = make_memory_tensor( |
| 99 | sg.name + "_scratch", scratch_area, MemType.Scratch, scratch_size, False, arch |
| 100 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 101 | sg.scratch_tensor.purpose = TensorPurpose.Scratch |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 102 | sg.flash_tensor = make_memory_tensor( |
| 103 | sg.name + "_flash", flash_area, MemType.Permanent_CPU, flash_size, True, arch |
| 104 | ) |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 105 | # Scratch fast tensor size set to 0. This forces a minimal allocation in the tensor arena |
| 106 | # which causes a slot in the basep registers to be reserved, so that the scratch fast tensor |
| 107 | # address can be overridden. |
| 108 | sg.scratch_fast_tensor = make_memory_tensor( |
| 109 | sg.name + "_scratch_fast", scratch_fast_area, MemType.Scratch, 0, False, arch |
| 110 | ) |
| 111 | sg.scratch_fast_tensor.purpose = TensorPurpose.Scratch |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 112 | else: |
| 113 | sg.scratch_tensor = scratch_tens |
| 114 | sg.scratch_tensor.shape[0] += scratch_size |
| 115 | sg.flash_tensor = flash_tens |
| 116 | sg.flash_tensor.shape[0] += flash_size |
| 117 | |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 118 | sg.scratch_fast_tensor = scratch_fast_tens |
| 119 | sg.scratch_fast_tensor.shape[0] = 0 |
| 120 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 121 | for cps in sg.cascaded_passes: |
| 122 | for ps in cps.passes: |
Charles Xu | 7879222 | 2020-05-13 10:15:26 +0200 | [diff] [blame] | 123 | if ps.placement == PassPlacement.Npu: |
Tim Hall | c30f495 | 2020-06-15 20:47:35 +0100 | [diff] [blame] | 124 | if ps.weight_tensor is not None: |
Charles Xu | 7879222 | 2020-05-13 10:15:26 +0200 | [diff] [blame] | 125 | # For DMA ops, ps.weight_tensor is referring to the SRAM weight tensor and therefore the address |
| 126 | # is pointing at the destination address of where the weights should be placed in SRAM. |
| 127 | # This ensures that the Flash weight tensor is used instead and thus gets the correct address. |
| 128 | if ps.weight_tensor.ops[0].type == "DMA": |
| 129 | copy_compressed_values_to_memory_tensor(sg.flash_tensor, ps.weight_tensor.ops[0].inputs[0]) |
| 130 | else: |
| 131 | copy_compressed_values_to_memory_tensor(sg.flash_tensor, ps.weight_tensor) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 132 | |
Charles Xu | 7879222 | 2020-05-13 10:15:26 +0200 | [diff] [blame] | 133 | copy_compressed_values_to_memory_tensor(sg.flash_tensor, ps.scale_tensor) |
| 134 | |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 135 | if ps.lut_tensor is not None: |
| 136 | copy_ifm_values_to_memory_tensor(sg.flash_tensor, ps.lut_tensor) |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 137 | if ps.ifm_tensor is not None and ps.ifm_tensor.mem_type not in (MemType.Scratch, MemType.Scratch_fast): |
Charles Xu | 7879222 | 2020-05-13 10:15:26 +0200 | [diff] [blame] | 138 | copy_ifm_values_to_memory_tensor(sg.flash_tensor, ps.ifm_tensor) |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 139 | if ps.ifm2_tensor is not None and ( |
| 140 | ps.ifm2_tensor.mem_type not in (MemType.Scratch, MemType.Scratch_fast) |
| 141 | ): |
Charles Xu | 7879222 | 2020-05-13 10:15:26 +0200 | [diff] [blame] | 142 | copy_ifm_values_to_memory_tensor(sg.flash_tensor, ps.ifm2_tensor) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 143 | |
| 144 | sg.command_stream_tensor = make_memory_tensor( |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 145 | sg.name + "_command_stream", flash_area, MemType.Permanent_CPU, command_stream_size_bytes, True, arch |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 146 | ) |
| 147 | sg.command_stream_tensor.values = np.frombuffer(payload_bytes, dtype=np.uint8) |
| 148 | |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 149 | return sg.scratch_tensor, sg.scratch_fast_tensor, sg.flash_tensor |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 150 | |
| 151 | |
| 152 | def add_const_tens_to_startup_cascaded_pass(startup_cps, tens): |
| 153 | op = Operation("Const", tens.name + "_const") |
Michael McGeagh | c5b549b | 2020-08-07 11:54:28 +0100 | [diff] [blame] | 154 | op.set_output_tensor(tens) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 155 | startup_cps.passes[0].ops.insert(0, op) |
| 156 | startup_cps.passes[0].outputs.insert(0, tens) |
| 157 | startup_cps.outputs.insert(0, tens) |
| 158 | |
| 159 | |
| 160 | def rewrite_npu_call_ops(nng, sg, arch): |
| 161 | if sg.placement != PassPlacement.Cpu: |
| 162 | return |
| 163 | |
| 164 | startup_cps = sg.cascaded_passes[0] |
| 165 | |
| 166 | for idx, cps in enumerate(sg.cascaded_passes): |
| 167 | for ps in cps.passes: |
| 168 | for op in ps.ops: |
| 169 | if op.type == "NpuOp": |
| 170 | callee = op.attrs["subgraph"] |
Tim Hall | c8310b1 | 2020-06-17 14:53:11 +0100 | [diff] [blame] | 171 | op.attrs["custom_type"] = op.type |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 172 | |
| 173 | sz = 0 |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 174 | for tens in [ |
| 175 | callee.scratch_fast_tensor, |
| 176 | callee.scratch_tensor, |
| 177 | callee.flash_tensor, |
| 178 | callee.command_stream_tensor, |
| 179 | ]: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 180 | op.inputs.insert(0, tens) |
| 181 | ps.inputs.insert(0, tens) |
| 182 | cps.inputs.insert(0, tens) |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 183 | if tens != callee.scratch_tensor and tens != callee.scratch_fast_tensor: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 184 | add_const_tens_to_startup_cascaded_pass(startup_cps, tens) |
| 185 | sz += tens.storage_size() |
| 186 | |
| 187 | for prev_cps in sg.cascaded_passes[: idx + 1]: |
| 188 | prev_cps.sram_used += sz |
| 189 | |
| 190 | if callee.scratch_tensor is not None: |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 191 | if callee.scratch_tensor.mem_area == MemArea.Sram: |
| 192 | cps.sram_used += callee.scratch_tensor.storage_size() |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 193 | |
| 194 | if callee.scratch_fast_tensor is not None: |
| 195 | if callee.scratch_fast_tensor.mem_area == MemArea.Sram: |
| 196 | cps.sram_used += callee.scratch_fast_tensor.storage_size() |