alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | #---------------------------------------------------------------------------- |
| 2 | # Copyright (c) 2021 Arm Limited. All rights reserved. |
| 3 | # SPDX-License-Identifier: Apache-2.0 |
| 4 | # |
| 5 | # Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | # you may not use this file except in compliance with the License. |
| 7 | # You may obtain a copy of the License at |
| 8 | # |
| 9 | # http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | # |
| 11 | # Unless required by applicable law or agreed to in writing, software |
| 12 | # distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | # See the License for the specific language governing permissions and |
| 15 | # limitations under the License. |
| 16 | #---------------------------------------------------------------------------- |
| 17 | |
| 18 | # CMake configuration file for peripheral memory map for simple platform. This is a stripped down |
| 19 | # version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However, |
| 20 | # for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of |
| 21 | # the CMSDK UART block used by the MPS3 FPGA and FVP implementations. |
Kshitij Sisodia | f4962c8 | 2021-10-04 12:20:33 +0100 | [diff] [blame] | 22 | ################################################################################################### |
| 23 | # Mem sizes # |
| 24 | ################################################################################################### |
| 25 | set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB") |
| 26 | set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks") |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 27 | set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB") |
| 28 | set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB") |
| 29 | set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB") |
Kshitij Sisodia | f4962c8 | 2021-10-04 12:20:33 +0100 | [diff] [blame] | 30 | set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB") |
| 31 | |
| 32 | ################################################################################################### |
| 33 | # Base addresses for memory regions # |
| 34 | ################################################################################################### |
| 35 | set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address") |
| 36 | set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address") |
| 37 | set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address") |
| 38 | set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address") |
| 39 | set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address") |
| 40 | set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address") |
| 41 | set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address") |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 42 | set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address") |
Kshitij Sisodia | f4962c8 | 2021-10-04 12:20:33 +0100 | [diff] [blame] | 43 | set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address") |
| 44 | set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address") |
| 45 | set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address") |
| 46 | set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address") |
| 47 | set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address") |
| 48 | |
| 49 | set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address") |
| 50 | set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address") |
| 51 | set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address") |
| 52 | set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address") |
| 53 | set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address") |
| 54 | set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address") |
| 55 | set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address") |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 56 | set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address") |
Kshitij Sisodia | f4962c8 | 2021-10-04 12:20:33 +0100 | [diff] [blame] | 57 | set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address") |
| 58 | set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address") |
| 59 | set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address") |
| 60 | set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 61 | |
| 62 | ################################################################################################### |
| 63 | # Application specific config # |
| 64 | ################################################################################################### |
| 65 | |
Kshitij Sisodia | 659fcd9 | 2021-05-19 10:30:06 +0100 | [diff] [blame] | 66 | # This parameter is based on the linker/scatter script for simple platform. Do not change this |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 67 | # parameter in isolation. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 68 | set(DESIGN_NAME "Simple platform" CACHE STRING "Design name") |
| 69 | |
Kshitij Sisodia | f4962c8 | 2021-10-04 12:20:33 +0100 | [diff] [blame] | 70 | # SRAM size reserved for activation buffers |
| 71 | math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL) |
| 72 | |
| 73 | |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 74 | ################################################################################################### |
| 75 | # Base addresses # |
| 76 | ################################################################################################### |
| 77 | set(PL011_UART0_BASE "0x49303000" CACHE STRING "PL011 UART 0 Base Address") |
| 78 | |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 79 | if (ETHOS_U_NPU_ENABLED) |
| 80 | set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address") |
| 81 | set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") |
| 82 | set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") |
| 83 | set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address") |
| 84 | set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") |
| 85 | set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 86 | endif () |
| 87 | |
| 88 | ################################################################################################### |
| 89 | # IRQ numbers # |
| 90 | ################################################################################################### |
Cisco Cervellera | f085fa5 | 2021-08-02 09:32:07 +0100 | [diff] [blame] | 91 | if (ETHOS_U_NPU_ENABLED) |
| 92 | set(EthosU_IRQn "56" CACHE STRING "Ethos-U NPU Interrupt") |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 93 | endif () |