Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 1 | /* |
Per Åstrand | 0fd65ce | 2021-03-11 10:25:18 +0100 | [diff] [blame] | 2 | * Copyright (c) 2019-2021 Arm Limited. All rights reserved. |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /***************************************************************************** |
| 20 | * Includes |
| 21 | *****************************************************************************/ |
| 22 | |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 23 | #include "ethosu_device.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 24 | #include "ethosu_driver.h" |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 25 | #include "ethosu_interface.h" |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 26 | #include "ethosu_log.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 27 | #include "pmu_ethosu.h" |
| 28 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 29 | #include <assert.h> |
Per Åstrand | e07b1f9 | 2020-09-28 08:31:46 +0200 | [diff] [blame] | 30 | #include <inttypes.h> |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 31 | #include <stddef.h> |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 32 | |
| 33 | /***************************************************************************** |
| 34 | * Defines |
| 35 | *****************************************************************************/ |
| 36 | |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 37 | #define MASK_0_31_BITS (0xFFFFFFFF) |
| 38 | #define MASK_32_47_BITS (0xFFFF00000000) |
| 39 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 40 | #define COMMA , |
| 41 | #define SEMICOLON ; |
| 42 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 43 | #define EVTYPE(A, name) \ |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 44 | case PMU_EVENT_##name: \ |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 45 | return ETHOSU_PMU_##name |
| 46 | |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 47 | #define EVID(A, name) (PMU_EVENT_##name) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 48 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 49 | /***************************************************************************** |
| 50 | * Variables |
| 51 | *****************************************************************************/ |
| 52 | |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 53 | static const enum pmu_event eventbyid[] = {EXPAND_PMU_EVENT(EVID, COMMA)}; |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 54 | |
| 55 | /***************************************************************************** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 56 | * Static functions |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 57 | *****************************************************************************/ |
| 58 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 59 | static enum ethosu_pmu_event_type pmu_event_type(uint32_t id) |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 60 | { |
| 61 | switch (id) |
| 62 | { |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 63 | EXPAND_PMU_EVENT(EVTYPE, SEMICOLON); |
Per Åstrand | e07b1f9 | 2020-09-28 08:31:46 +0200 | [diff] [blame] | 64 | default: |
| 65 | LOG_ERR("Unknown PMU event id: 0x%" PRIx32 "\n", id); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | return ETHOSU_PMU_SENTINEL; |
| 69 | } |
| 70 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 71 | static uint32_t pmu_event_value(enum ethosu_pmu_event_type event) |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 72 | { |
Per Åstrand | 51c18ba | 2020-09-28 11:25:36 +0200 | [diff] [blame] | 73 | int a = event; |
| 74 | if ((a < ETHOSU_PMU_SENTINEL) && (a >= ETHOSU_PMU_NO_EVENT)) |
| 75 | { |
| 76 | return eventbyid[event]; |
| 77 | } |
| 78 | else |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 79 | { |
| 80 | return (uint32_t)(-1); |
| 81 | } |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 82 | } |
| 83 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 84 | /***************************************************************************** |
| 85 | * Functions |
| 86 | *****************************************************************************/ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 87 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 88 | void ETHOSU_PMU_Enable(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 89 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 90 | LOG_DEBUG("Enable PMU\n"); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 91 | struct pmcr_r pmcr = {0}; |
| 92 | pmcr.cnt_en = 1; |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 93 | set_clock_and_power_request(drv, ETHOSU_PMU_REQUEST, ETHOSU_CLOCK_Q_DISABLE, ETHOSU_POWER_Q_DISABLE); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 94 | drv->dev->reg->PMCR.word = pmcr.word; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 95 | } |
| 96 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 97 | void ETHOSU_PMU_Disable(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 98 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 99 | LOG_DEBUG("Disable PMU\n"); |
Anton Moberg | 0a61429 | 2021-03-24 14:08:22 +0100 | [diff] [blame] | 100 | set_clock_and_power_request(drv, ETHOSU_PMU_REQUEST, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_ENABLE); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 101 | drv->dev->reg->PMCR.word = 0; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 102 | } |
| 103 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 104 | void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 105 | { |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 106 | assert(num < ETHOSU_PMU_NCOUNTERS); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 107 | uint32_t val = pmu_event_value(type); |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 108 | LOG_DEBUG("num=%u, type=%d, val=%u\n", num, type, val); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 109 | drv->dev->reg->PMEVTYPER[num].word = val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 110 | } |
| 111 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 112 | enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 113 | { |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 114 | assert(num < ETHOSU_PMU_NCOUNTERS); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 115 | uint32_t val = drv->dev->reg->PMEVTYPER[num].word; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 116 | enum ethosu_pmu_event_type type = pmu_event_type(val); |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 117 | LOG_DEBUG("num=%u, type=%d, val=%u\n", num, type, val); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 118 | return type; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 119 | } |
| 120 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 121 | void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 122 | { |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 123 | LOG_DEBUG("Reset PMU cycle counter\n"); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 124 | struct pmcr_r pmcr; |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 125 | pmcr.word = drv->dev->reg->PMCR.word; |
| 126 | pmcr.cycle_cnt_rst = 1; |
| 127 | drv->dev->reg->PMCR.word = pmcr.word; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 128 | } |
| 129 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 130 | void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 131 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 132 | LOG_DEBUG("Reset all events\n"); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 133 | struct pmcr_r pmcr; |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 134 | pmcr.word = drv->dev->reg->PMCR.word; |
| 135 | pmcr.event_cnt_rst = 1; |
| 136 | drv->dev->reg->PMCR.word = pmcr.word; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 137 | } |
| 138 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 139 | void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 140 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 141 | LOG_DEBUG("mask=0x%08x\n", mask); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 142 | drv->dev->reg->PMCNTENSET.word = mask; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 143 | } |
| 144 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 145 | void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 146 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 147 | LOG_DEBUG("mask=0x%08x\n", mask); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 148 | drv->dev->reg->PMCNTENCLR.word = mask; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 149 | } |
| 150 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 151 | uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 152 | { |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 153 | uint32_t pmcntenset = drv->dev->reg->PMCNTENSET.word; |
| 154 | LOG_DEBUG("mask=0x%08x\n", pmcntenset); |
| 155 | return pmcntenset; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 156 | } |
| 157 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 158 | uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 159 | { |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 160 | uint32_t val_lo = drv->dev->reg->PMCCNTR.CYCLE_CNT_LO; |
| 161 | uint32_t val_hi = drv->dev->reg->PMCCNTR.CYCLE_CNT_HI; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 162 | uint64_t val = ((uint64_t)val_hi << 32) | val_lo; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 163 | |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 164 | LOG_DEBUG("val=%" PRIu64 "\n", val); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 165 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 166 | } |
| 167 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 168 | void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 169 | { |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 170 | uint32_t active = ETHOSU_PMU_CNTR_Status(drv) & ETHOSU_PMU_CCNT_Msk; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 171 | |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 172 | LOG_DEBUG("val=%llu\n", val); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 173 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 174 | if (active) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 175 | { |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 176 | ETHOSU_PMU_CNTR_Disable(drv, ETHOSU_PMU_CCNT_Msk); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 177 | } |
| 178 | |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 179 | drv->dev->reg->PMCCNTR.CYCLE_CNT_LO = val & MASK_0_31_BITS; |
| 180 | drv->dev->reg->PMCCNTR.CYCLE_CNT_HI = (val & MASK_32_47_BITS) >> 32; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 181 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 182 | if (active) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 183 | { |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 184 | ETHOSU_PMU_CNTR_Enable(drv, ETHOSU_PMU_CCNT_Msk); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 185 | } |
| 186 | } |
| 187 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 188 | uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 189 | { |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 190 | assert(num < ETHOSU_PMU_NCOUNTERS); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 191 | uint32_t val = drv->dev->reg->PMEVCNTR[num].word; |
| 192 | LOG_DEBUG("num=%u, val=%u\n", num, val); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 193 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 194 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 195 | } |
| 196 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 197 | void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 198 | { |
Kristofer Jonsson | 1c893b5 | 2021-05-26 12:06:14 +0200 | [diff] [blame] | 199 | assert(num < ETHOSU_PMU_NCOUNTERS); |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 200 | LOG_DEBUG("num=%u, val=%u\n", num, val); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 201 | drv->dev->reg->PMEVCNTR[num].word = val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 202 | } |
| 203 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 204 | uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 205 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 206 | LOG_DEBUG(""); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 207 | return drv->dev->reg->PMOVSSET.word; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 208 | } |
| 209 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 210 | void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 211 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 212 | LOG_DEBUG(""); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 213 | drv->dev->reg->PMOVSCLR.word = mask; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 214 | } |
| 215 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 216 | void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 217 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 218 | LOG_DEBUG("mask=0x%08x\n", mask); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 219 | drv->dev->reg->PMINTSET.word = mask; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 220 | } |
| 221 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 222 | void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 223 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 224 | LOG_DEBUG("mask=0x%08x\n", mask); |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 225 | drv->dev->reg->PMINTCLR.word = mask; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 226 | } |
| 227 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 228 | uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 229 | { |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 230 | uint32_t pmint = drv->dev->reg->PMINTSET.word; |
| 231 | LOG_DEBUG("mask=0x%08x\n", pmint); |
| 232 | return pmint; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 233 | } |
| 234 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 235 | void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 236 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 237 | LOG_DEBUG(""); |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 238 | uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(drv); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 239 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 240 | // Disable counters |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 241 | ETHOSU_PMU_CNTR_Disable(drv, mask); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 242 | |
| 243 | // Increment cycle counter |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 244 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 245 | { |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 246 | uint64_t val = ETHOSU_PMU_Get_CCNTR(drv) + 1; |
| 247 | drv->dev->reg->PMCCNTR.CYCLE_CNT_LO = val & MASK_0_31_BITS; |
| 248 | drv->dev->reg->PMCCNTR.CYCLE_CNT_HI = (val & MASK_32_47_BITS) >> 32; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 249 | } |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 250 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 251 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 252 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 253 | if (mask & (1 << i)) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 254 | { |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 255 | uint32_t val = ETHOSU_PMU_Get_EVCNTR(drv, i); |
| 256 | drv->dev->reg->PMEVCNTR[i].word = val + 1; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 257 | } |
| 258 | } |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 259 | |
| 260 | // Reenable the active counters |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 261 | ETHOSU_PMU_CNTR_Enable(drv, cntrs_active); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 262 | } |
| 263 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 264 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 265 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 266 | LOG_DEBUG("start_event=%u\n", start_event); |
Per Åstrand | 0fd65ce | 2021-03-11 10:25:18 +0100 | [diff] [blame] | 267 | uint32_t val = pmu_event_value(start_event); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 268 | struct pmccntr_cfg_r cfg; |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 269 | cfg.word = drv->dev->reg->PMCCNTR_CFG.word; |
| 270 | cfg.CYCLE_CNT_CFG_START = val; |
| 271 | drv->dev->reg->PMCCNTR_CFG.word = cfg.word; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 272 | } |
| 273 | |
Anton Moberg | c6fd88e | 2021-05-03 17:00:33 +0200 | [diff] [blame] | 274 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 275 | { |
Anton Moberg | 6eab40b | 2021-07-07 11:43:51 +0200 | [diff] [blame] | 276 | LOG_DEBUG("stop_event=%u\n", stop_event); |
Per Åstrand | 0fd65ce | 2021-03-11 10:25:18 +0100 | [diff] [blame] | 277 | uint32_t val = pmu_event_value(stop_event); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 278 | struct pmccntr_cfg_r cfg; |
Jonny Svärd | 136810f | 2021-10-13 16:04:26 +0200 | [diff] [blame^] | 279 | cfg.word = drv->dev->reg->PMCCNTR_CFG.word; |
| 280 | cfg.CYCLE_CNT_CFG_STOP = val; |
| 281 | drv->dev->reg->PMCCNTR_CFG.word = cfg.word; |
| 282 | } |