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Kristofer Jonsson49bdee82020-04-06 13:21:21 +02001/*
2 * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
Kristofer Jonsson3c439172020-08-05 09:38:40 +020019#ifndef ETHOSU_DEVICE_H
20#define ETHOSU_DEVICE_H
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020021
22/******************************************************************************
23 * Includes
24 ******************************************************************************/
25
Bhavik Patel5da40922020-07-15 10:06:43 +020026#include "pmu_ethosu.h"
27
28#include <stdbool.h>
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020029#include <stdint.h>
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
35/******************************************************************************
36 * Defines
37 ******************************************************************************/
38
39#define ETHOSU_DRIVER_VERSION_MAJOR 0 ///< Driver major version
Douglas Trohaf6a85da2020-05-11 11:45:28 +020040#define ETHOSU_DRIVER_VERSION_MINOR 16 ///< Driver minor version
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020041#define ETHOSU_DRIVER_VERSION_PATCH 0 ///< Driver patch version
42#define ETHOSU_DRIVER_BASEP_INDEXES 8 ///< Number of base pointer indexes
43
44/******************************************************************************
45 * Types
46 ******************************************************************************/
47
48enum ethosu_error_codes
49{
50 ETHOSU_SUCCESS = 0, ///< Success
51 ETHOSU_GENERIC_FAILURE = -1, ///< Generic failure
52 ETHOSU_INVALID_PARAM = -2 ///< Invalid parameter
53};
54
Bhavik Pateldae5be02020-06-18 15:25:15 +020055struct ethosu_device
56{
57 uintptr_t base_address;
Bhavik Patel5f8dad12020-09-30 09:06:52 +020058 uint32_t reset;
Kristofer Jonssonef387ea2020-08-25 16:32:21 +020059 uint32_t pmcr;
Bhavik Patel5da40922020-07-15 10:06:43 +020060 uint64_t pmccntr;
Kristofer Jonssonef387ea2020-08-25 16:32:21 +020061 uint32_t pmcnten;
62 uint32_t pmint;
63 uint32_t pmccntr_cfg;
Bhavik Patel5da40922020-07-15 10:06:43 +020064 uint32_t pmu_evcntr[ETHOSU_PMU_NCOUNTERS];
65 enum ethosu_pmu_event_type pmu_evtypr[ETHOSU_PMU_NCOUNTERS];
Bhavik Pateldae5be02020-06-18 15:25:15 +020066};
67
Kristofer Jonsson49bdee82020-04-06 13:21:21 +020068struct ethosu_id
69{
70 uint32_t version_status; ///< Version status
71 uint32_t version_minor; ///< Version minor
72 uint32_t version_major; ///< Version major
73 uint32_t product_major; ///< Product major
74 uint32_t arch_patch_rev; ///< Architecture version patch
75 uint32_t arch_minor_rev; ///< Architecture version minor
76 uint32_t arch_major_rev; ///< Architecture version major
77};
78
79struct ethosu_config
80{
81 struct
82 {
83 uint32_t macs_per_cc; ///< MACs per clock cycle
84 uint32_t cmd_stream_version; ///< NPU command stream version
85 uint32_t shram_size; ///< SHRAM size
86 };
87};
88
89/**
90 * Memory type parameter for set_regioncfg_reg:
91 * Counter{0,1}: Outstanding transactions for
92 * AXI port 0 for memory type/region a=0,b=1
93 * Counter{2,3}: Outstanding transactions for
94 * AXI port 1 for memory type/region a=2,b=3
95 */
96enum ethosu_memory_type
97{
98 ETHOSU_AXI0_OUTSTANDING_COUNTER0 = 0, ///< NPU axi0_outstanding_counter0
99 ETHOSU_AXI0_OUTSTANDING_COUNTER1 = 1, ///< NPU axi0_outstanding_counter1
100 ETHOSU_AXI1_OUTSTANDING_COUNTER2 = 2, ///< NPU axi1_outstanding_counter2
101 ETHOSU_AXI1_OUTSTANDING_COUNTER3 = 3 ///< NPU axi1_outstanding_counter3
102};
103
104enum ethosu_axi_limit_beats
105{
106 ETHOSU_AXI_LIMIT_64_BYTES = 0, ///< NPU AXI limit 64 byte burst split alignment.
107 ETHOSU_AXI_LIMIT_128_BYTES = 1, ///< NPU AXI limit 128 byte burst split alignment.
108 ETHOSU_AXI_LIMIT_256_BYTES = 2 ///< NPU AXI limit 256 byte burst split alignment.
109};
110
111enum ethosu_axi_limit_mem_type
112{
113 ETHOSU_MEM_TYPE_DEVICE_NON_BUFFERABLE = 0,
114 ETHOSU_MEM_TYPE_DEVICE_BUFFERABLE = 1,
115 ETHOSU_MEM_TYPE_NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2,
116 ETHOSU_MEM_TYPE_NORMAL_NON_CACHEABLE_BUFFERABLE = 3,
117 ETHOSU_MEM_TYPE_WRITE_THROUGH_NO_ALLOCATE = 4,
118 ETHOSU_MEM_TYPE_WRITE_THROUGH_READ_ALLOCATE = 5,
119 ETHOSU_MEM_TYPE_WRITE_THROUGH_WRITE_ALLOCATE = 6,
120 ETHOSU_MEM_TYPE_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7,
121 ETHOSU_MEM_TYPE_WRITE_BACK_NO_ALLOCATE = 8,
122 ETHOSU_MEM_TYPE_WRITE_BACK_READ_ALLOCATE = 9,
123 ETHOSU_MEM_TYPE_WRITE_BACK_WRITE_ALLOCATE = 10,
124 ETHOSU_MEM_TYPE_WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11
125};
126
127enum ethosu_clock_q_request
128{
129 ETHOSU_CLOCK_Q_DISABLE = 0, ///< Disble NPU signal ready for clock off.
130 ETHOSU_CLOCK_Q_ENABLE = 1 ///< Enable NPU signal ready for clock off when stop+idle state reached.
131};
132
133enum ethosu_power_q_request
134{
135 ETHOSU_POWER_Q_DISABLE = 0, ///< Disble NPU signal ready for power off.
136 ETHOSU_POWER_Q_ENABLE = 1 ///< Enable NPU signal ready for power off when stop+idle state reached.
137};
138
139/******************************************************************************
140 * Prototypes
141 ******************************************************************************/
142
143/**
144 * Initialize the device.
145 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200146enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev, const void *base_address);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200147
148/**
149 * Get device id.
150 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200151enum ethosu_error_codes ethosu_get_id(struct ethosu_device *dev, struct ethosu_id *id);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200152
153/**
154 * Get device configuration.
155 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200156enum ethosu_error_codes ethosu_get_config(struct ethosu_device *dev, struct ethosu_config *config);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200157
158/**
159 * Execute a given command stream on NPU.
160 * \param[in] cmd_stream_ptr Pointer to the command stream
161 * \param[in] cms_length Command stream length
162 * \param[in] base_addr Pointer to array of base addresses
163 * - 0: weight tensor
164 * - 1: scratch tensor
165 * - All input tensors
166 * - All output tensors
167 * \param[in] num_base_addr Number of base addresses.
168 * \return \ref ethosu_error_codes
169 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200170enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev,
171 const uint8_t *cmd_stream_ptr,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200172 uint32_t cms_length,
173 const uint64_t *base_addr,
174 int num_base_addr);
175
176/**
177 * Check if IRQ is raised.
178 * \param[out] irq_status Pointer to IRQ status
179 * - 0 IRQ not raised
180 * - 1 IRQ raised
181 * \return \ref ethosu_error_codes
182 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200183enum ethosu_error_codes ethosu_is_irq_raised(struct ethosu_device *dev, uint8_t *irq_status);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200184
185/**
186 * Clear IRQ status.
187 * \return \ref ethosu_error_codes
188 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200189enum ethosu_error_codes ethosu_clear_irq_status(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200190
191/**
192 * Get the 16 bit status mask.
193 * \param[out] irq_status_mask Pointer to the status mask.
194 * The lower 16 bits of status reg are returned.
195 * bit0: state
196 * bit1: irq_raised
197 * bit2: bus_status
198 * bit3: reset_status
199 * bit4: cmd_parse_error
200 * bit5: cmd_end_reached
201 * bit6: pmu_irq_raised
202 * bit7-15: reserved
203 * \return \ref ethosu_error_codes
204 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200205enum ethosu_error_codes ethosu_get_status_mask(struct ethosu_device *dev, uint16_t *status_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200206
207/**
208 * Get the 16 bit IRQ history mask.
209 * \param[out] irq_history_mask Pointer to the IRQ history mask.
210 * \return \ref ethosu_error_codes
211 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200212enum ethosu_error_codes ethosu_get_irq_history_mask(struct ethosu_device *dev, uint16_t *irq_history_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200213
214/**
215 * Clear the given bits in the
216 * IRQ history mask.
217 * \param[in] irq_history_clear_mask 16 bit mask indicating which bits to
218 * clear in the IRQ history mask.
219 * \return \ref ethosu_error_codes
220 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200221enum ethosu_error_codes ethosu_clear_irq_history_mask(struct ethosu_device *dev, uint16_t irq_history_clear_mask);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200222
223/**
224 * Perform a NPU soft reset.
225 * \return \ref ethosu_error_codes
226 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200227enum ethosu_error_codes ethosu_soft_reset(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200228
229/**
230 * Wait for reset ready.
231 * \return \ref ethosu_error_codes
232 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200233enum ethosu_error_codes ethosu_wait_for_reset(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200234
235/**
236 * Read and return the content of a given NPU APB
237 * register range.
238 * \param[in] start_address Start address.
239 * \param[in] num_reg Number of registers to read.
240 * \param[out] reg_p Pointer to a output area, allocated by the
241 * caller, where the register content shall be
242 * written.
243 * \return \ref ethosu_error_codes
244 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200245enum ethosu_error_codes ethosu_read_apb_reg(struct ethosu_device *dev,
246 uint32_t start_address,
247 uint16_t num_reg,
248 uint32_t *reg_p);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200249
250/**
251 * Set qconfig register. I.e.
252 * AXI configuration for the command stream.
253 * \param[in] memory_type Memory_type to use for command stream:
254 * enum ethosu_memory_type.
255 * \return \ref ethosu_error_codes
256 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200257enum ethosu_error_codes ethosu_set_qconfig(struct ethosu_device *dev, enum ethosu_memory_type memory_type);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200258
259/**
260 * Set register REGIONCFG.
261 * Base pointer configuration.
262 * Bits[2*k+1:2*k] give the memory type for BASEP[k].
263 * \param[in] region Region field to set: 0 - 7.
264 * \param[in] memory_type Memory_type to use for region: enum ethosu_memory_type.
265 * \return \ref ethosu_error_codes
266 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200267enum ethosu_error_codes ethosu_set_regioncfg(struct ethosu_device *dev,
268 uint8_t region,
269 enum ethosu_memory_type memory_type);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200270
271/**
272 * Set AXI limit parameters for port 0 counter 0.
273 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
274 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
275 * \param[in] max_reads Maximum number of outstanding reads.
276 * \param[in] max_writes Maximum number of outstanding writes.
277 * \return \ref ethosu_error_codes
278 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200279enum ethosu_error_codes ethosu_set_axi_limit0(struct ethosu_device *dev,
280 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200281 enum ethosu_axi_limit_mem_type memtype,
282 uint8_t max_reads,
283 uint8_t max_writes);
284/**
285 * Set AXI limit parameters for port 0 counter 1.
286 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
287 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
288 * \param[in] max_reads Maximum number of outstanding reads.
289 * \param[in] max_writes Maximum number of outstanding writes.
290 * \return \ref ethosu_error_codes
291 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200292enum ethosu_error_codes ethosu_set_axi_limit1(struct ethosu_device *dev,
293 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200294 enum ethosu_axi_limit_mem_type memtype,
295 uint8_t max_reads,
296 uint8_t max_writes);
297/**
298 * Set AXI limit parameters for port 1 counter 2.
299 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
300 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
301 * \param[in] max_reads Maximum number of outstanding reads.
302 * \param[in] max_writes Maximum number of outstanding writes.
303 * \return \ref ethosu_error_codes
304 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200305enum ethosu_error_codes ethosu_set_axi_limit2(struct ethosu_device *dev,
306 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200307 enum ethosu_axi_limit_mem_type memtype,
308 uint8_t max_reads,
309 uint8_t max_writes);
310/**
311 * Set AXI limit parameters for port 1 counter 3.
312 * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats.
313 * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type
314 * \param[in] max_reads Maximum number of outstanding reads.
315 * \param[in] max_writes Maximum number of outstanding writes.
316 * \return \ref ethosu_error_codes
317 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200318enum ethosu_error_codes ethosu_set_axi_limit3(struct ethosu_device *dev,
319 enum ethosu_axi_limit_beats max_beats,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200320 enum ethosu_axi_limit_mem_type memtype,
321 uint8_t max_reads,
322 uint8_t max_writes);
323
324/**
325 * Get current command stream queue read position.
326 * \param[out] qread Pointer to queue read.
327 * \return \ref ethosu_error_codes
328 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200329enum ethosu_error_codes ethosu_get_qread(struct ethosu_device *dev, uint32_t *qread);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200330
331/**
332 * Get revision of NPU
333 * \param[out] revision Pointer to revision read.
334 * \return \ref ethosu_error_codes
335 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200336enum ethosu_error_codes ethosu_get_revision(struct ethosu_device *dev, uint32_t *revision);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200337
338/**
339 * Issue run command for the currently programmed
340 * command stream, starting at current queue read
341 * position.
342 * \return \ref ethosu_error_codes
343 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200344enum ethosu_error_codes ethosu_set_command_run(struct ethosu_device *dev);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200345
346/**
347 * Dump a 1KB section of SHRAM.
348 * \param[in] section Section offset to 1KB section in SHRAM.
349 * \param[out] shram_p Pointer to a output area, allocated by the
350 * caller, where the SHRAM content shall be
351 * written.
352 * \return \ref ethosu_error_codes
353 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200354enum ethosu_error_codes ethosu_get_shram_data(struct ethosu_device *dev, int section, uint32_t *shram_p);
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200355
356/**
357 * Set clock and power q request enable bits.
358 * \param[in] clock_q Clock q ENABLE/DISABLE \ref clock_q_request.
359 * \param[in] power_q Power q ENABLE/DISABLE \ref power_q_request.
360 * \return \ref ethosu_error_codes
361 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200362enum ethosu_error_codes ethosu_set_clock_and_power(struct ethosu_device *dev,
363 enum ethosu_clock_q_request clock_q,
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200364 enum ethosu_power_q_request power_q);
365
Kristofer Jonsson3c439172020-08-05 09:38:40 +0200366/**
367 * Read register.
368 * \param[in] address Address to read.
369 * \return Register value.
370 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200371uint32_t ethosu_read_reg(struct ethosu_device *dev, uint32_t address);
372
Kristofer Jonsson3c439172020-08-05 09:38:40 +0200373/**
374 * Write register.
375 * \param[in] address Address to read.
376 * \param[in] value Value to be written.
377 */
Bhavik Pateldae5be02020-06-18 15:25:15 +0200378void ethosu_write_reg(struct ethosu_device *dev, uint32_t address, uint32_t value);
379
Bhavik Patel5da40922020-07-15 10:06:43 +0200380/**
381 * Save the PMU configuration to ethosu_device struct.
382 * \param[in] dev Ethos-U device where the PMU configuration is
383 * saved.
384 * \return \ref ethosu_error_codes
385 */
386enum ethosu_error_codes ethosu_save_pmu_config(struct ethosu_device *dev);
387
388/**
389 * Restore the PMU configuration from a ethosu_device struct.
390 * \param[in] dev Ethos-U device where the PMU configuration is
391 * stored.
392 * \return \ref ethosu_error_codes
393 */
394enum ethosu_error_codes ethosu_restore_pmu_config(struct ethosu_device *dev);
395
Bhavik Patel5f8dad12020-09-30 09:06:52 +0200396/**
397 * Check if the STATUS register has any error bits set or not.
398 * \param[in] dev Ethos-U device to check.
399 * \return true if any error bits set,
400 * false otherwise.
401 */
402bool ethosu_status_has_error(struct ethosu_device *dev);
403
Kristofer Jonsson49bdee82020-04-06 13:21:21 +0200404#ifdef __cplusplus
405}
406#endif
Kristofer Jonsson3c439172020-08-05 09:38:40 +0200407
408#endif // ETHOSU_DEVICE_H