Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /***************************************************************************** |
| 20 | * Includes |
| 21 | *****************************************************************************/ |
| 22 | |
| 23 | #include "ethosu55_interface.h" |
| 24 | #include "ethosu_common.h" |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 25 | #include "ethosu_driver.h" |
| 26 | #include "pmu_ethosu.h" |
| 27 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 28 | #include <assert.h> |
Per Åstrand | e07b1f9 | 2020-09-28 08:31:46 +0200 | [diff] [blame] | 29 | #include <inttypes.h> |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 30 | #include <stddef.h> |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 31 | |
| 32 | /***************************************************************************** |
| 33 | * Defines |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | #define COMMA , |
| 37 | #define SEMICOLON ; |
| 38 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 39 | #define EVTYPE(A, name) \ |
| 40 | case PMU_EVENT_TYPE_##name: \ |
| 41 | return ETHOSU_PMU_##name |
| 42 | |
| 43 | #define EVID(A, name) (PMU_EVENT_TYPE_##name) |
| 44 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 45 | #define NPU_REG_PMEVCNTR(x) (NPU_REG_PMEVCNTR0 + ((x) * sizeof(uint32_t))) |
| 46 | #define NPU_REG_PMEVTYPER(x) (NPU_REG_PMEVTYPER0 + ((x) * sizeof(uint32_t))) |
| 47 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 48 | /***************************************************************************** |
| 49 | * Variables |
| 50 | *****************************************************************************/ |
| 51 | |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 52 | static const enum pmu_event_type eventbyid[] = {EXPAND_PMU_EVENT_TYPE(EVID, COMMA)}; |
| 53 | |
| 54 | /***************************************************************************** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 55 | * Static functions |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 56 | *****************************************************************************/ |
| 57 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 58 | static enum ethosu_pmu_event_type pmu_event_type(uint32_t id) |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 59 | { |
| 60 | switch (id) |
| 61 | { |
| 62 | EXPAND_PMU_EVENT_TYPE(EVTYPE, SEMICOLON); |
Per Åstrand | e07b1f9 | 2020-09-28 08:31:46 +0200 | [diff] [blame] | 63 | default: |
| 64 | LOG_ERR("Unknown PMU event id: 0x%" PRIx32 "\n", id); |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | return ETHOSU_PMU_SENTINEL; |
| 68 | } |
| 69 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 70 | static uint32_t pmu_event_value(enum ethosu_pmu_event_type event) |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 71 | { |
Per Åstrand | 51c18ba | 2020-09-28 11:25:36 +0200 | [diff] [blame] | 72 | int a = event; |
| 73 | if ((a < ETHOSU_PMU_SENTINEL) && (a >= ETHOSU_PMU_NO_EVENT)) |
| 74 | { |
| 75 | return eventbyid[event]; |
| 76 | } |
| 77 | else |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 78 | { |
| 79 | return (uint32_t)(-1); |
| 80 | } |
Kristofer Jonsson | 537c71c | 2020-05-05 14:17:22 +0200 | [diff] [blame] | 81 | } |
| 82 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 83 | /***************************************************************************** |
| 84 | * Functions |
| 85 | *****************************************************************************/ |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 86 | |
| 87 | void ETHOSU_PMU_Enable(void) |
| 88 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 89 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 90 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 91 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 92 | pmcr.cnt_en = 1; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 93 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word, ðosu_drv.dev.pmcr); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | void ETHOSU_PMU_Disable(void) |
| 97 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 98 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 99 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 100 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 101 | pmcr.cnt_en = 0; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 102 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word, ðosu_drv.dev.pmcr); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | void ETHOSU_PMU_Set_EVTYPER(uint32_t num, enum ethosu_pmu_event_type type) |
| 106 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 107 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 108 | uint32_t val = pmu_event_value(type); |
| 109 | LOG_DEBUG("%s: num=%u, type=%d, val=%u\n", __FUNCTION__, num, type, val); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 110 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMEVTYPER(num), val, ðosu_drv.dev.pmu_evtypr[num]); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(uint32_t num) |
| 114 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 115 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 116 | uint32_t val = ethosu_drv.dev.pmu_evtypr[num]; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 117 | enum ethosu_pmu_event_type type = pmu_event_type(val); |
| 118 | LOG_DEBUG("%s: num=%u, type=%d, val=%u\n", __FUNCTION__, num, type, val); |
| 119 | return type; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | void ETHOSU_PMU_CYCCNT_Reset(void) |
| 123 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 124 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 125 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 126 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 127 | pmcr.cycle_cnt_rst = 1; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 128 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word, ðosu_drv.dev.pmcr); |
| 129 | ethosu_drv.dev.pmccntr[0] = 0; |
| 130 | ethosu_drv.dev.pmccntr[1] = 0; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | void ETHOSU_PMU_EVCNTR_ALL_Reset(void) |
| 134 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 135 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 136 | struct pmcr_r pmcr; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 137 | pmcr.word = ethosu_drv.dev.pmcr; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 138 | pmcr.event_cnt_rst = 1; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 139 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCR, pmcr.word, ðosu_drv.dev.pmcr); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 140 | |
| 141 | for (uint32_t i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 142 | { |
| 143 | ethosu_drv.dev.pmu_evcntr[i] = 0; |
| 144 | } |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | void ETHOSU_PMU_CNTR_Enable(uint32_t mask) |
| 148 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 149 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 150 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCNTENSET, mask, ðosu_drv.dev.pmcnten); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | void ETHOSU_PMU_CNTR_Disable(uint32_t mask) |
| 154 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 155 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 156 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCNTENCLR, mask, ðosu_drv.dev.pmcnten); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 157 | } |
| 158 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 159 | uint32_t ETHOSU_PMU_CNTR_Status(void) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 160 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 161 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, ethosu_drv.dev.pmcnten); |
| 162 | return ethosu_drv.dev.pmcnten; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | uint64_t ETHOSU_PMU_Get_CCNTR(void) |
| 166 | { |
Kristofer Jonsson | bad5a49 | 2020-10-23 10:45:30 +0200 | [diff] [blame] | 167 | uint32_t val_lo = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_LO); |
| 168 | uint32_t val_hi = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMCCNTR_HI); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 169 | uint64_t val = ((uint64_t)val_hi << 32) | val_lo; |
| 170 | uint64_t shadow = ((uint64_t)ethosu_drv.dev.pmccntr[1] << 32) | ethosu_drv.dev.pmccntr[0]; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 171 | |
Kristofer Jonsson | bad5a49 | 2020-10-23 10:45:30 +0200 | [diff] [blame] | 172 | LOG_DEBUG("%s: val=%" PRIu64 ", shadow=%" PRIu64 "\n", __FUNCTION__, val, shadow); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 173 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 174 | // Return the shadow variable in case the NPU was powered off and lost the cycle count |
| 175 | if (shadow > val) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 176 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 177 | return shadow; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 178 | } |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 179 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 180 | // Update the shadow variable |
| 181 | ethosu_drv.dev.pmccntr[0] = val_lo; |
| 182 | ethosu_drv.dev.pmccntr[1] = val_hi; |
| 183 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 184 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | void ETHOSU_PMU_Set_CCNTR(uint64_t val) |
| 188 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 189 | uint32_t active = ETHOSU_PMU_CNTR_Status() & ETHOSU_PMU_CCNT_Msk; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 190 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 191 | LOG_DEBUG("%s: val=%llu\n", __FUNCTION__, val); |
| 192 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 193 | if (active) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 194 | { |
| 195 | ETHOSU_PMU_CNTR_Disable(ETHOSU_PMU_CCNT_Msk); |
| 196 | } |
| 197 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 198 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, val & MASK_0_31_BITS, ðosu_drv.dev.pmccntr[0]); |
| 199 | ethosu_write_reg_shadow( |
| 200 | ðosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32, ðosu_drv.dev.pmccntr[1]); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 201 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 202 | if (active) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 203 | { |
| 204 | ETHOSU_PMU_CNTR_Enable(ETHOSU_PMU_CCNT_Msk); |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | uint32_t ETHOSU_PMU_Get_EVCNTR(uint32_t num) |
| 209 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 210 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 211 | uint32_t val = ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(num)); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 212 | LOG_DEBUG("%s: num=%u, val=%u, shadow=%u\n", __FUNCTION__, num, val, ethosu_drv.dev.pmu_evcntr[num]); |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 213 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 214 | // Return the shadow variable in case the NPU was powered off and lost the event count |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 215 | if (ethosu_drv.dev.pmu_evcntr[num] > val) |
| 216 | { |
| 217 | return ethosu_drv.dev.pmu_evcntr[num]; |
| 218 | } |
| 219 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 220 | // Update the shadow variable |
| 221 | ethosu_drv.dev.pmu_evcntr[num] = val; |
| 222 | |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 223 | return val; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | void ETHOSU_PMU_Set_EVCNTR(uint32_t num, uint32_t val) |
| 227 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 228 | ASSERT(num < ETHOSU_PMU_NCOUNTERS); |
| 229 | LOG_DEBUG("%s: num=%u, val=%u\n", __FUNCTION__, num, val); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 230 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMEVCNTR(num), val); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | uint32_t ETHOSU_PMU_Get_CNTR_OVS(void) |
| 234 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 235 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 236 | return ethosu_read_reg(ðosu_drv.dev, NPU_REG_PMOVSSET); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 237 | } |
| 238 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 239 | void ETHOSU_PMU_Set_CNTR_OVS(uint32_t mask) |
| 240 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 241 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 242 | ethosu_write_reg(ðosu_drv.dev, NPU_REG_PMOVSCLR, mask); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | void ETHOSU_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) |
| 246 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 247 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 248 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMINTSET, mask, ðosu_drv.dev.pmint); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | void ETHOSU_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) |
| 252 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 253 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, mask); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 254 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMINTCLR, mask, ðosu_drv.dev.pmint); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 255 | } |
| 256 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 257 | uint32_t ETHOSU_PMU_Get_IRQ_Enable(void) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 258 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 259 | LOG_DEBUG("%s: mask=0x%08x\n", __FUNCTION__, ethosu_drv.dev.pmint); |
| 260 | return ethosu_drv.dev.pmint; |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | void ETHOSU_PMU_CNTR_Increment(uint32_t mask) |
| 264 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 265 | LOG_DEBUG("%s:\n", __FUNCTION__); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 266 | uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(); |
| 267 | |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 268 | // Disable counters |
| 269 | ETHOSU_PMU_CNTR_Disable(mask); |
| 270 | |
| 271 | // Increment cycle counter |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 272 | if (mask & ETHOSU_PMU_CCNT_Msk) |
| 273 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 274 | uint64_t val = ETHOSU_PMU_Get_CCNTR() + 1; |
| 275 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCCNTR_LO, val & MASK_0_31_BITS, ðosu_drv.dev.pmccntr[0]); |
| 276 | ethosu_write_reg_shadow( |
| 277 | ðosu_drv.dev, NPU_REG_PMCCNTR_HI, (val & MASK_32_47_BITS) >> 32, ðosu_drv.dev.pmccntr[1]); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 278 | } |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 279 | |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 280 | for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) |
| 281 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 282 | if (mask & (1 << i)) |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 283 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 284 | uint32_t val = ETHOSU_PMU_Get_EVCNTR(i); |
| 285 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMEVCNTR(i), val + 1, ðosu_drv.dev.pmu_evcntr[i]); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 286 | } |
| 287 | } |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 288 | |
| 289 | // Reenable the active counters |
| 290 | ETHOSU_PMU_CNTR_Enable(cntrs_active); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(uint32_t start_event) |
| 294 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 295 | LOG_DEBUG("%s: start_event=%u\n", __FUNCTION__, start_event); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 296 | struct pmccntr_cfg_r cfg; |
| 297 | cfg.word = ethosu_drv.dev.pmccntr_cfg; |
| 298 | cfg.CYCLE_CNT_CFG_START = start_event; |
| 299 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg.word, ðosu_drv.dev.pmccntr_cfg); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(uint32_t stop_event) |
| 303 | { |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 304 | LOG_DEBUG("%s: stop_event=%u\n", __FUNCTION__, stop_event); |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 305 | struct pmccntr_cfg_r cfg; |
| 306 | cfg.word = ethosu_drv.dev.pmccntr_cfg; |
| 307 | cfg.CYCLE_CNT_CFG_STOP = stop_event; |
| 308 | ethosu_write_reg_shadow(ðosu_drv.dev, NPU_REG_PMCCNTR_CFG, cfg.word, ðosu_drv.dev.pmccntr_cfg); |
Bhavik Patel | 8e32b0b | 2020-06-23 13:48:25 +0200 | [diff] [blame] | 309 | } |