Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 1 | /* |
Anton Moberg | fa3e51b | 2021-03-31 11:05:02 +0200 | [diff] [blame] | 2 | * Copyright (c) 2020-2021 Arm Limited. All rights reserved. |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
| 19 | /**************************************************************************** |
| 20 | * Includes |
| 21 | ****************************************************************************/ |
| 22 | |
| 23 | #include "target.hpp" |
| 24 | |
| 25 | #ifdef ETHOSU |
| 26 | #include <ethosu_driver.h> |
| 27 | #endif |
| 28 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 29 | #include "mpu.hpp" |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 30 | #include <timing_adapter.h> |
| 31 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 32 | #include "uart.h" |
| 33 | |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 34 | #include <inttypes.h> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 35 | #include <stdio.h> |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 36 | #include <stdlib.h> |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 37 | #include <vector> |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 38 | |
| 39 | using namespace EthosU; |
| 40 | |
| 41 | /**************************************************************************** |
| 42 | * Defines |
| 43 | ****************************************************************************/ |
| 44 | |
| 45 | #define ETHOSU_BASE_ADDRESS 0x48102000 |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 46 | #define ETHOSU_IRQ 56 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 47 | |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 48 | #define ETHOSU0_TA0_BASE_ADDRESS 0x48103000 |
| 49 | #define ETHOSU0_TA1_BASE_ADDRESS 0x48103200 |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 50 | |
| 51 | /**************************************************************************** |
| 52 | * Variables |
| 53 | ****************************************************************************/ |
| 54 | |
| 55 | #if defined(ETHOSU_FAST_MEMORY_SIZE) && ETHOSU_FAST_MEMORY_SIZE > 0 |
| 56 | __attribute__((aligned(16), section(".bss.ethosu_scratch"))) uint8_t ethosu_scratch[ETHOSU_FAST_MEMORY_SIZE]; |
| 57 | #else |
| 58 | #define ethosu_scratch 0 |
| 59 | #define ETHOSU_FAST_MEMORY_SIZE 0 |
| 60 | #endif |
| 61 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 62 | #ifdef ETHOSU |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame^] | 63 | struct ethosu_driver ethosu0_driver; |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 64 | #endif |
| 65 | |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 66 | static uintptr_t ethosu_ta_base_addrs[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT] = { |
| 67 | {ETHOSU0_TA0_BASE_ADDRESS, ETHOSU0_TA1_BASE_ADDRESS}}; |
| 68 | struct timing_adapter ethosu_ta[ETHOSU_NPU_COUNT][ETHOSU_NPU_TA_COUNT]; |
| 69 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 70 | /**************************************************************************** |
| 71 | * Cache maintenance |
| 72 | ****************************************************************************/ |
| 73 | |
| 74 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 75 | extern "C" { |
| 76 | void ethosu_flush_dcache(uint32_t *p, size_t bytes) { |
| 77 | if (p) |
| 78 | SCB_CleanDCache_by_Addr(p, bytes); |
| 79 | else |
| 80 | SCB_CleanDCache(); |
| 81 | } |
| 82 | |
| 83 | void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) { |
| 84 | if (p) |
| 85 | SCB_InvalidateDCache_by_Addr(p, bytes); |
| 86 | else |
| 87 | SCB_InvalidateDCache(); |
| 88 | } |
| 89 | } |
| 90 | #endif |
| 91 | |
| 92 | /**************************************************************************** |
| 93 | * Init |
| 94 | ****************************************************************************/ |
| 95 | |
| 96 | namespace { |
| 97 | |
Per Åstrand | 174e98d | 2021-02-09 17:48:53 +0100 | [diff] [blame] | 98 | extern "C" { |
| 99 | struct ExcContext { |
| 100 | uint32_t r0; |
| 101 | uint32_t r1; |
| 102 | uint32_t r2; |
| 103 | uint32_t r3; |
| 104 | uint32_t r12; |
| 105 | uint32_t lr; |
| 106 | uint32_t pc; |
| 107 | uint32_t xPsr; |
| 108 | }; |
| 109 | |
| 110 | void HardFault_Handler() { |
| 111 | int irq; |
| 112 | struct ExcContext *e; |
| 113 | uint32_t sp; |
| 114 | |
| 115 | asm volatile("mrs %0, ipsr \n" // Read IPSR (Exceptio number) |
| 116 | "sub %0, #16 \n" // Get it into IRQn_Type range |
| 117 | "tst lr, #4 \n" // Select the stack which was in use |
| 118 | "ite eq \n" |
| 119 | "mrseq %1, msp \n" |
| 120 | "mrsne %1, psp \n" |
| 121 | "mov %2, sp \n" |
| 122 | : "=r"(irq), "=r"(e), "=r"(sp)); |
| 123 | |
| 124 | printf("Hard fault. irq=%d, pc=0x%08" PRIx32 ", lr=0x%08" PRIx32 ", xpsr=0x%08" PRIx32 ", sp=0x%08" PRIx32 "\n", |
| 125 | irq, |
| 126 | e->pc, |
| 127 | e->lr, |
| 128 | e->xPsr, |
| 129 | sp); |
| 130 | printf( |
| 131 | "%11s cfsr=0x%08" PRIx32 " bfar=0x%08" PRIx32 " mmfar=0x%08" PRIx32 "\n", "", SCB->CFSR, SCB->BFAR, SCB->MMFAR); |
| 132 | exit(1); |
| 133 | } |
| 134 | } |
| 135 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 136 | #ifdef ETHOSU |
| 137 | void ethosuIrqHandler() { |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame^] | 138 | ethosu_irq_handler(ðosu0_driver); |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 139 | } |
| 140 | #endif |
| 141 | |
| 142 | } // namespace |
| 143 | |
| 144 | namespace EthosU { |
| 145 | |
| 146 | void targetSetup() { |
| 147 | // Initialize UART driver |
| 148 | uart_init(); |
| 149 | |
Jonny Svärd | d667090 | 2021-03-18 15:49:27 +0100 | [diff] [blame] | 150 | // Initialize timing adapter(s) |
| 151 | for (int i = 0; i < ETHOSU_NPU_COUNT; i++) { |
| 152 | for (int j = 0; j < ETHOSU_NPU_TA_COUNT; j++) { |
| 153 | if (ta_init(ðosu_ta[i][j], ethosu_ta_base_addrs[i][j])) { |
| 154 | printf("Failed to initialize timing-adapter %d for NPU %d\n", j, i); |
| 155 | } |
| 156 | } |
| 157 | } |
| 158 | |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 159 | #ifdef ETHOSU |
| 160 | // Initialize Ethos-U NPU driver |
Jonny Svärd | c5941c4 | 2021-06-01 18:40:45 +0200 | [diff] [blame^] | 161 | if (ethosu_init(ðosu0_driver, |
Anton Moberg | ebe9a15 | 2021-05-03 09:28:52 +0200 | [diff] [blame] | 162 | reinterpret_cast<void *>(ETHOSU_BASE_ADDRESS), |
| 163 | ethosu_scratch, |
| 164 | ETHOSU_FAST_MEMORY_SIZE, |
| 165 | 1, |
| 166 | 1)) { |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 167 | printf("Failed to initialize NPU.\n"); |
| 168 | return; |
| 169 | } |
| 170 | |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 171 | // Assumes SCB->VTOR point to RW memory |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 172 | NVIC_SetVector(static_cast<IRQn_Type>(ETHOSU_IRQ), (uint32_t)ðosuIrqHandler); |
| 173 | NVIC_EnableIRQ(static_cast<IRQn_Type>(ETHOSU_IRQ)); |
| 174 | #endif |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 175 | |
| 176 | // MPU setup |
| 177 | const std::vector<ARM_MPU_Region_t> mpuConfig = { |
| 178 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 179 | // ITCM (NS) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 180 | ARM_MPU_RBAR(0x00000000, // Base |
| 181 | ARM_MPU_SH_NON, // Non-shareable |
| 182 | 1, // Read-Only |
| 183 | 1, // Non-Privileged |
| 184 | 0), // eXecute Never disabled |
| 185 | ARM_MPU_RLAR(0x0007ffff, // Limit |
| 186 | Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate |
| 187 | }, |
| 188 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 189 | // ITCM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 190 | ARM_MPU_RBAR(0x10000000, // Base |
| 191 | ARM_MPU_SH_NON, // Non-shareable |
| 192 | 1, // Read-Only |
| 193 | 1, // Non-Privileged |
| 194 | 0), // eXecute Never disabled |
| 195 | ARM_MPU_RLAR(0x1007ffff, // Limit |
| 196 | Mpu::WTRA_index) // Attribute index - Write-Through, Read-allocate |
| 197 | }, |
| 198 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 199 | // FPGA DATA SRAM; BRAM (NS) |
| 200 | ARM_MPU_RBAR(0x01000000, // Base |
| 201 | ARM_MPU_SH_NON, // Non-shareable |
| 202 | 0, // Read-Write |
| 203 | 1, // Non-Privileged |
| 204 | 0), // eXecute Never disabled |
| 205 | ARM_MPU_RLAR(0x011fffff, // Limit |
| 206 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 207 | }, |
| 208 | { |
| 209 | // FPGA DATA SRAM; BRAM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 210 | ARM_MPU_RBAR(0x11000000, // Base |
| 211 | ARM_MPU_SH_NON, // Non-shareable |
| 212 | 0, // Read-Write |
| 213 | 1, // Non-Privileged |
| 214 | 0), // eXecute Never disabled |
| 215 | ARM_MPU_RLAR(0x111fffff, // Limit |
| 216 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 217 | }, |
| 218 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 219 | // DTCM (NS) |
| 220 | ARM_MPU_RBAR(0x20000000, // Base |
| 221 | ARM_MPU_SH_NON, // Non-shareable |
| 222 | 0, // Read-Write |
| 223 | 1, // Non-Privileged |
| 224 | 1), // eXecute Never enabled |
| 225 | ARM_MPU_RLAR(0x2007ffff, // Limit |
| 226 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 227 | }, |
| 228 | { |
| 229 | // DTCM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 230 | ARM_MPU_RBAR(0x30000000, // Base |
| 231 | ARM_MPU_SH_NON, // Non-shareable |
| 232 | 0, // Read-Write |
| 233 | 1, // Non-Privileged |
| 234 | 1), // eXecute Never enabled |
| 235 | ARM_MPU_RLAR(0x3007ffff, // Limit |
| 236 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 237 | }, |
| 238 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 239 | // SSE-300 internal SRAM (NS) |
| 240 | ARM_MPU_RBAR(0x21000000, // Base |
| 241 | ARM_MPU_SH_NON, // Non-shareable |
| 242 | 0, // Read-Write |
| 243 | 1, // Non-Privileged |
| 244 | 1), // eXecute Never enabled |
| 245 | ARM_MPU_RLAR(0x213fffff, // Limit |
| 246 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 247 | }, |
| 248 | { |
| 249 | // SSE-300 internal SRAM (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 250 | ARM_MPU_RBAR(0x31000000, // Base |
| 251 | ARM_MPU_SH_NON, // Non-shareable |
| 252 | 0, // Read-Write |
| 253 | 1, // Non-Privileged |
| 254 | 1), // eXecute Never enabled |
| 255 | ARM_MPU_RLAR(0x313fffff, // Limit |
| 256 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 257 | }, |
| 258 | { |
Jonny Svärd | e3b6b96 | 2021-04-27 11:32:31 +0200 | [diff] [blame] | 259 | // DDR (NS) |
| 260 | ARM_MPU_RBAR(0x60000000, // Base |
| 261 | ARM_MPU_SH_NON, // Non-shareable |
| 262 | 0, // Read-Write |
| 263 | 1, // Non-Privileged |
| 264 | 1), // eXecute Never enabled |
| 265 | ARM_MPU_RLAR(0x6fffffff, // Limit |
| 266 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 267 | }, |
| 268 | { |
| 269 | // DDR (S) |
Jonny Svärd | 991af2b | 2021-04-15 17:31:01 +0200 | [diff] [blame] | 270 | ARM_MPU_RBAR(0x70000000, // Base |
| 271 | ARM_MPU_SH_NON, // Non-shareable |
| 272 | 0, // Read-Write |
| 273 | 1, // Non-Privileged |
| 274 | 1), // eXecute Never enabled |
| 275 | ARM_MPU_RLAR(0x7fffffff, // Limit |
| 276 | Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate |
| 277 | }}; |
| 278 | |
| 279 | // Setup MPU configuration |
| 280 | Mpu::loadAndEnableConfig(&mpuConfig[0], mpuConfig.size()); |
| 281 | |
| 282 | #if defined(CPU_CACHE_ENABLE) && defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) |
| 283 | SCB_EnableICache(); |
| 284 | SCB_EnableDCache(); |
| 285 | #endif |
Kristofer Jonsson | f62c3d7 | 2021-01-21 17:39:03 +0100 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | } // namespace EthosU |