Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 1 | ; Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. |
| 2 | ; |
| 3 | ; SPDX-License-Identifier: Apache-2.0 |
| 4 | ; |
| 5 | ; Licensed under the Apache License, Version 2.0 (the License); you may |
| 6 | ; not use this file except in compliance with the License. |
| 7 | ; You may obtain a copy of the License at |
| 8 | ; |
| 9 | ; www.apache.org/licenses/LICENSE-2.0 |
| 10 | ; |
| 11 | ; Unless required by applicable law or agreed to in writing, software |
| 12 | ; distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 13 | ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | ; See the License for the specific language governing permissions and |
| 15 | ; limitations under the License. |
| 16 | |
| 17 | ; ----------------------------------------------------------------------------- |
| 18 | ; Vela configuration file |
| 19 | |
| 20 | ; ----------------------------------------------------------------------------- |
| 21 | ; System Configuration |
| 22 | |
| 23 | ; Ethos-U55 Deep Embedded: SRAM (1.6 GB/s) and Flash (0.1 GB/s) |
| 24 | [System_Config.Ethos_U55_Deep_Embedded] |
| 25 | core_clock=200e6 |
| 26 | axi0_port=Sram |
| 27 | axi1_port=OffChipFlash |
| 28 | Sram_clock_scale=1.0 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 29 | Sram_burst_length=32 |
| 30 | Sram_read_latency=32 |
| 31 | Sram_write_latency=32 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 32 | OffChipFlash_clock_scale=0.0625 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 33 | OffChipFlash_burst_length=128 |
| 34 | OffChipFlash_read_latency=64 |
| 35 | OffChipFlash_write_latency=64 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 36 | |
| 37 | ; Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s) |
| 38 | [System_Config.Ethos_U55_High_End_Embedded] |
| 39 | core_clock=500e6 |
| 40 | axi0_port=Sram |
| 41 | axi1_port=OffChipFlash |
| 42 | Sram_clock_scale=1.0 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 43 | Sram_burst_length=32 |
| 44 | Sram_read_latency=32 |
| 45 | Sram_write_latency=32 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 46 | OffChipFlash_clock_scale=0.125 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 47 | OffChipFlash_burst_length=128 |
| 48 | OffChipFlash_read_latency=64 |
| 49 | OffChipFlash_write_latency=64 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 50 | |
| 51 | ; Ethos-U65 Embedded: SRAM (8 GB/s) and Flash (0.5 GB/s) |
| 52 | [System_Config.Ethos_U65_Embedded] |
| 53 | core_clock=500e6 |
| 54 | axi0_port=Sram |
| 55 | axi1_port=OffChipFlash |
| 56 | Sram_clock_scale=1.0 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 57 | Sram_burst_length=32 |
| 58 | Sram_read_latency=32 |
| 59 | Sram_write_latency=32 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 60 | OffChipFlash_clock_scale=0.0625 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 61 | OffChipFlash_burst_length=128 |
| 62 | OffChipFlash_read_latency=64 |
| 63 | OffChipFlash_write_latency=64 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 64 | |
| 65 | ; Ethos-U65 Mid-End: SRAM (8 GB/s) and DRAM (3.75 GB/s) |
| 66 | [System_Config.Ethos_U65_Mid_End] |
| 67 | core_clock=500e6 |
| 68 | axi0_port=Sram |
| 69 | axi1_port=Dram |
| 70 | Sram_clock_scale=1.0 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 71 | Sram_burst_length=32 |
| 72 | Sram_read_latency=32 |
| 73 | Sram_write_latency=32 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 74 | Dram_clock_scale=0.46875 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 75 | Dram_burst_length=128 |
| 76 | Dram_read_latency=500 |
| 77 | Dram_write_latency=250 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 78 | |
| 79 | ; Ethos-U65 High-End: SRAM (16 GB/s) and DRAM (3.75 GB/s) |
| 80 | [System_Config.Ethos_U65_High_End] |
| 81 | core_clock=1e9 |
| 82 | axi0_port=Sram |
| 83 | axi1_port=Dram |
| 84 | Sram_clock_scale=1.0 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 85 | Sram_burst_length=32 |
| 86 | Sram_read_latency=32 |
| 87 | Sram_write_latency=32 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 88 | Dram_clock_scale=0.234375 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 89 | Dram_burst_length=128 |
| 90 | Dram_read_latency=500 |
| 91 | Dram_write_latency=250 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 92 | |
| 93 | ; Ethos-U65 Client-Server: SRAM (16 GB/s) and DRAM (12 GB/s) |
| 94 | [System_Config.Ethos_U65_Client_Server] |
| 95 | core_clock=1e9 |
| 96 | axi0_port=Sram |
| 97 | axi1_port=Dram |
| 98 | Sram_clock_scale=1.0 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 99 | Sram_burst_length=32 |
| 100 | Sram_read_latency=32 |
| 101 | Sram_write_latency=32 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 102 | Dram_clock_scale=0.75 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 103 | Dram_burst_length=128 |
| 104 | Dram_read_latency=500 |
| 105 | Dram_write_latency=250 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 106 | |
| 107 | ; ----------------------------------------------------------------------------- |
| 108 | ; Memory Mode |
| 109 | |
| 110 | ; SRAM Only: only one AXI port is used and the SRAM is used for all storage |
| 111 | [Memory_Mode.Sram_Only] |
| 112 | const_mem_area=Axi0 |
| 113 | arena_mem_area=Axi0 |
| 114 | cache_mem_area=Axi0 |
| 115 | |
Tim Hall | 70b71a5 | 2020-12-22 11:47:54 +0000 | [diff] [blame] | 116 | ; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 117 | ; The non-SRAM memory is assumed to be read-only |
| 118 | [Memory_Mode.Shared_Sram] |
| 119 | const_mem_area=Axi1 |
| 120 | arena_mem_area=Axi0 |
| 121 | cache_mem_area=Axi0 |
| 122 | |
| 123 | ; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U |
| 124 | ; The non-SRAM memory is assumed to be read-writeable |
| 125 | [Memory_Mode.Dedicated_Sram] |
| 126 | const_mem_area=Axi1 |
| 127 | arena_mem_area=Axi1 |
| 128 | cache_mem_area=Axi0 |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 129 | arena_cache_size=393216 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 130 | |
| 131 | ; Dedicated SRAM 512KB: the SRAM (512KB) is only for use by the Ethos-U |
| 132 | ; The non-SRAM memory is assumed to be read-writeable |
| 133 | [Memory_Mode.Dedicated_Sram_512KB] |
| 134 | inherit=Memory_Mode.Dedicated_Sram |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 135 | arena_cache_size=524288 |