Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1 | # Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. |
| 2 | # |
| 3 | # SPDX-License-Identifier: Apache-2.0 |
| 4 | # |
| 5 | # Licensed under the Apache License, Version 2.0 (the License); you may |
| 6 | # not use this file except in compliance with the License. |
| 7 | # You may obtain a copy of the License at |
| 8 | # |
| 9 | # www.apache.org/licenses/LICENSE-2.0 |
| 10 | # |
| 11 | # Unless required by applicable law or agreed to in writing, software |
| 12 | # distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 13 | # WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | # See the License for the specific language governing permissions and |
| 15 | # limitations under the License. |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 16 | # Description: |
| 17 | # Register level (low-level) command stream generation for Ethos-U55. Takes a high-level command stream and generates |
| 18 | # all the register settings. Calculates dependencies between commands and inserts wait operations. And generates a bit |
| 19 | # stream suitable for interpretation by the Ethos-U55 processor. |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 20 | from collections import defaultdict |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 21 | from collections import namedtuple |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 22 | from enum import Enum |
| 23 | from enum import IntEnum |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 24 | |
| 25 | import numpy as np |
| 26 | |
| 27 | from . import scaling |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 28 | from .architecture_features import ArchitectureFeatures |
| 29 | from .architecture_features import Block |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 30 | from .architecture_features import Rect |
| 31 | from .architecture_features import SharedBufferArea |
| 32 | from .architecture_features import SHRAMElements |
| 33 | from .data_type import BaseType |
| 34 | from .data_type import DataType |
| 35 | from .ethos_u55_regs.ethos_u55_regs import acc_format |
| 36 | from .ethos_u55_regs.ethos_u55_regs import activation |
| 37 | from .ethos_u55_regs.ethos_u55_regs import cmd0 |
| 38 | from .ethos_u55_regs.ethos_u55_regs import cmd1 |
| 39 | from .ethos_u55_regs.ethos_u55_regs import elementwise_mode |
| 40 | from .ethos_u55_regs.ethos_u55_regs import ifm_precision |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 41 | from .ethos_u55_regs.ethos_u55_regs import pooling_mode |
Jacob Bohlin | cf7da10 | 2020-05-20 09:03:40 +0200 | [diff] [blame] | 42 | from .ethos_u55_regs.ethos_u55_regs import resampling_mode |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 43 | from .ethos_u55_regs.ethos_u55_regs import rounding |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 44 | from .high_level_command_stream import CommandType |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 45 | from .numeric_util import clamp_sigmoid |
| 46 | from .numeric_util import clamp_tanh |
Louis Verhaard | b2fb212 | 2020-06-04 15:51:24 +0200 | [diff] [blame] | 47 | from .numeric_util import full_shape |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 48 | from .numeric_util import quantise_float32 |
| 49 | from .numeric_util import round_away_zero |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 50 | from .numeric_util import round_up_to_int |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 51 | from .operation import NpuBlockType |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 52 | from .operation import Op |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 53 | from .tensor import MemType |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 54 | from .tensor import TensorBlockTraversal |
| 55 | from .tensor import TensorFormat |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 56 | from .tensor import TensorPurpose |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 57 | |
| 58 | |
| 59 | class RegisterMachine: |
| 60 | def __init__(self): |
| 61 | self.n_banks = 1 |
| 62 | self.registers = [defaultdict(lambda: None) for _ in range(self.n_banks)] |
| 63 | self.bank_idx = 0 |
| 64 | |
| 65 | def set_register(self, reg, value): |
| 66 | is_changed = self.registers[self.bank_idx][reg] != value |
| 67 | self.registers[self.bank_idx][reg] = value |
| 68 | # is_changed = True # force command |
| 69 | return is_changed |
| 70 | |
| 71 | def switch_bank(self): |
| 72 | self.bank_idx = (self.bank_idx + 1) % self.n_banks |
| 73 | |
| 74 | |
| 75 | class CmdMode(IntEnum): |
| 76 | NoPayload = 0x0000 |
| 77 | Payload32 = 0x4000 |
| 78 | Mask = 0xC000 |
| 79 | CmdOpMask = 0x03FF |
| 80 | |
| 81 | |
| 82 | class BasePointerIndex(IntEnum): |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 83 | WeightTensor = 0 # base address index for the Weight tensor |
| 84 | ScratchTensor = 1 # base address index for the Scratch_tensor in the TensorArena |
| 85 | ScratchFastTensor = 2 # base address for the Scratch_fast_tensor |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 86 | Mem2Mem = (1 << 8) | (3 << 0) # base address slot for memory 2 memory transfer |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 87 | |
| 88 | |
| 89 | # TODO: Replace with definitions from ethos_u55_regs |
| 90 | class IFM2Broadcast(IntEnum): |
| 91 | BroadcastHdim = 1 << 0 |
| 92 | BroadcastWdim = 1 << 1 |
| 93 | BroadcastCdim = 1 << 2 |
| 94 | ReverseOperandOrder = 1 << 6 |
| 95 | UseIFM2Scalar = 1 << 7 |
| 96 | |
| 97 | |
| 98 | class CommandStreamEmitter: |
| 99 | def __init__(self): |
| 100 | self.cmd_stream = [] |
| 101 | self.reg_machine = [RegisterMachine(), RegisterMachine()] |
| 102 | self.last_absolute_wait = defaultdict(int) |
| 103 | |
| 104 | def get_reg_machine(self, cmd): |
| 105 | if "DMA" in cmd.name: |
| 106 | return self.reg_machine[1] |
| 107 | else: |
| 108 | return self.reg_machine[0] |
| 109 | |
| 110 | def size_in_bytes(self): |
| 111 | sz = 0 |
| 112 | for cmd in self.cmd_stream: |
| 113 | sz += len(cmd) * 4 |
| 114 | return sz |
| 115 | |
| 116 | def to_list(self): |
| 117 | return [elem for cmd in self.cmd_stream for elem in cmd] |
| 118 | |
| 119 | def print_cmds(self): |
| 120 | print("Code: Command: Param: Payload:") |
| 121 | for words_for_one_command in self.cmd_stream: |
| 122 | code = words_for_one_command[0] & 0x0000FFFF # lower 16 bits |
| 123 | param = words_for_one_command[0] >> 16 # higher 16 bits |
| 124 | |
| 125 | payload_mode = CmdMode(code & CmdMode.Mask) |
| 126 | |
| 127 | # code and command |
| 128 | s = " 0x%04x " % code |
| 129 | if payload_mode == CmdMode.NoPayload: |
| 130 | s += str(cmd0(code & CmdMode.CmdOpMask)) |
| 131 | else: |
| 132 | s += str(cmd1(code & CmdMode.CmdOpMask)) |
| 133 | |
| 134 | s = s.ljust(40) |
| 135 | s += "%5d" % param |
| 136 | |
| 137 | # payload |
| 138 | if payload_mode == CmdMode.Payload32: |
| 139 | s += " 0x%08x (%d)" % (words_for_one_command[1], words_for_one_command[1]) |
| 140 | else: |
| 141 | s += " -" |
| 142 | |
| 143 | print(s) |
| 144 | |
| 145 | def cmd0_with_param(self, cmd, param): |
| 146 | if isinstance(param, Enum): |
| 147 | param = int(param.value) |
| 148 | else: |
| 149 | param = int(param) |
| 150 | param = param & 0xFFFF |
| 151 | command = cmd.value | (param << 16) |
| 152 | if not self.get_reg_machine(cmd).set_register(cmd, (command, param)): |
| 153 | return |
| 154 | |
| 155 | # This is not a redundant command, actually write it |
| 156 | self.cmd_stream.append((command,)) |
| 157 | |
| 158 | def cmd1_with_offset(self, cmd, offset, param=0x0): |
| 159 | offset = int(offset) & 0xFFFFFFFFF |
| 160 | command = cmd.value | CmdMode.Payload32.value | (param << 16) |
| 161 | |
| 162 | if not self.get_reg_machine(cmd).set_register(cmd, (command, offset)): |
| 163 | return |
| 164 | |
| 165 | # This is not a redundant command, actually write it |
| 166 | self.cmd_stream.append((command, offset)) |
| 167 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 168 | def cmd_wait(self, cmd, channel, outstanding_count): |
| 169 | param = (16 * channel) + outstanding_count |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 170 | command = ((param & 0xFFFF) << 16) | cmd.value |
| 171 | self.cmd_stream.append((command,)) |
| 172 | |
| 173 | def cmd_do_operation(self, cmd, param=0): |
| 174 | param = int(param) |
| 175 | command = ((param & 0xFFFF) << 16) | cmd.value |
| 176 | |
| 177 | self.cmd_stream.append((command,)) |
| 178 | self.get_reg_machine(cmd).switch_bank() |
| 179 | |
| 180 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 181 | Watermark = namedtuple("Watermark", ["npu", "dma"]) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 182 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 183 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 184 | def get_cmd_wait_dependency(arch, cmd_stream, memory_accesses, cmd_index, watermark: Watermark): |
| 185 | cmd = cmd_stream[cmd_index] |
| 186 | cmd_access = memory_accesses[cmd] |
| 187 | index = cmd_index - 1 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 188 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 189 | # NPU dependency tracking |
| 190 | npu_outstanding = -1 |
| 191 | npu_ops = 0 |
| 192 | npu_index = watermark.npu |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 193 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 194 | # DMA dependency tracking |
| 195 | dma_outstanding = -1 |
| 196 | dma_ops = 0 |
| 197 | dma_index = watermark.dma |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 198 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 199 | # Seek back in the command stream looking for NPU or DMA dependencies |
| 200 | # but only as far as the first dependency or the watermarks (dependencies |
| 201 | # before this point have been satisfied already). |
| 202 | # The watermark moves to after the latest element we must wait for, not |
| 203 | # the command that issues the wait. |
| 204 | # NPU->NPU dependency is handled via blockdep. |
| 205 | while (index >= npu_index) or (index >= dma_index): |
| 206 | prev_cmd = cmd_stream[index] |
| 207 | prev_access = memory_accesses[prev_cmd] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 208 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 209 | # Check DMA consuming NPU output |
| 210 | if prev_cmd.cmdtype == CommandType.NpuStripe: |
| 211 | if index >= npu_index: |
| 212 | if (cmd.cmdtype == CommandType.DMA) and (npu_outstanding == -1) and prev_access.conflicts(cmd_access): |
| 213 | npu_outstanding = npu_ops |
| 214 | npu_ops = npu_ops + 1 # Count NPU ops in the pipeline |
| 215 | if npu_ops >= arch.max_outstanding_kernels: |
| 216 | npu_index = max(index + 1, npu_index) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 217 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 218 | # Check NPU consuming DMA output |
| 219 | elif prev_cmd.cmdtype == CommandType.DMA: |
| 220 | if index >= dma_index: |
| 221 | if cmd.cmdtype == CommandType.NpuStripe: |
| 222 | if (dma_outstanding == -1) and prev_access.conflicts(cmd_access): |
| 223 | dma_outstanding = dma_ops |
| 224 | dma_ops = dma_ops + 1 # Count DMA ops in the pipeline |
| 225 | if dma_ops >= arch.max_outstanding_dma: |
| 226 | dma_index = max(index + 1, dma_index) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 227 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 228 | index = index - 1 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 229 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 230 | # Update DMA watermark if we didn't see any and the NPU pipeline is full |
| 231 | if (dma_ops == 0) and (npu_ops >= arch.max_outstanding_kernels): |
| 232 | dma_index = cmd_index |
| 233 | |
| 234 | # Bring the search watermark forwards as we complete for those dependencies |
| 235 | watermark = Watermark(npu_index, dma_index) |
| 236 | outstanding = Watermark(npu_outstanding, dma_outstanding) |
| 237 | |
| 238 | return watermark, outstanding |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 239 | |
| 240 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 241 | def has_prev_op_dependency(prev_cmd, cmd): |
| 242 | if prev_cmd is None: |
| 243 | return False |
| 244 | if (prev_cmd.cmdtype == cmd.cmdtype == CommandType.NpuStripe) and (prev_cmd.ps != cmd.ps): |
Louis Verhaard | 0b8268a | 2020-08-05 16:11:29 +0200 | [diff] [blame] | 245 | if prev_cmd.ofm_tensor.equivalent(cmd.ifm_tensor): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 246 | return True |
Tim Hall | 9033795 | 2020-05-07 16:42:35 +0100 | [diff] [blame] | 247 | elif cmd.ifm2_tensor is not None: |
Louis Verhaard | 0b8268a | 2020-08-05 16:11:29 +0200 | [diff] [blame] | 248 | return prev_cmd.ofm_tensor.equivalent(cmd.ifm2_tensor) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 249 | return False |
| 250 | |
| 251 | |
| 252 | def get_op_ofm_rect(cmd): |
Charles Xu | 3e9c434 | 2020-04-22 08:31:43 +0200 | [diff] [blame] | 253 | start = full_shape(4, cmd.ofm_box.start_coord, 0) |
| 254 | end = full_shape(4, cmd.ofm_box.end_coord, 1) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 255 | return Rect(start[-2], start[-3], start[-1], end[-2] - 1, end[-3] - 1, end[-1] - 1) |
| 256 | |
| 257 | |
| 258 | def get_op_ifm_rect(cmd): |
Charles Xu | 3e9c434 | 2020-04-22 08:31:43 +0200 | [diff] [blame] | 259 | start = full_shape(4, cmd.ifm_box.start_coord, 0) |
| 260 | end = full_shape(4, cmd.ifm_box.end_coord, 1) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 261 | return Rect(start[-2], start[-3], start[-1], end[-2] - 1, end[-3] - 1, end[-1] - 1) |
| 262 | |
| 263 | |
| 264 | def get_op_ifmofm_block_depth(arch, cmd): |
| 265 | # Note: NOT equivalent to the normal ifm block depth calculation since |
| 266 | # it takes into account 'depthless' block operations by returning full |
| 267 | # depth |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 268 | if cmd.ps.npu_block_type in ( |
| 269 | NpuBlockType.ConvolutionDepthWise, |
| 270 | NpuBlockType.Pooling, |
| 271 | NpuBlockType.ElementWise, |
| 272 | NpuBlockType.ReduceSum, |
| 273 | ): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 274 | return cmd.ofm_box.get_size_shape()[-1] |
| 275 | |
| 276 | return arch.calc_ifm_block_depth(cmd.ifm_box.get_size_shape()[-1], cmd.ifm_tensor.dtype.bits) |
| 277 | |
| 278 | |
| 279 | def get_op_padding_lt(cmd): |
| 280 | if cmd.ps.npu_block_type not in ( |
| 281 | NpuBlockType.ConvolutionDepthWise, |
| 282 | NpuBlockType.Pooling, |
| 283 | NpuBlockType.ConvolutionMxN, |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 284 | NpuBlockType.ReduceSum, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 285 | ): |
| 286 | return (0, 0) |
| 287 | |
| 288 | explicit_padding = list(cmd.ps.primary_op.attrs["explicit_padding"]) # (top, left, bottom, right) |
| 289 | |
| 290 | # Check if this is for horizontal ifm streaming |
| 291 | if not (cmd.is_first_h_stripe and cmd.is_last_h_stripe): |
| 292 | explicit_padding[0] = cmd.pad_top |
| 293 | explicit_padding[2] = cmd.pad_bottom |
| 294 | |
| 295 | return (explicit_padding[1], explicit_padding[0]) |
| 296 | |
| 297 | |
Jacob Bohlin | e99b893 | 2020-07-13 16:01:51 +0200 | [diff] [blame] | 298 | def ifm_ifm2_correct_order(ifm_shape, ifm2_shape): |
| 299 | if ifm_shape == []: |
| 300 | # Scalar needs to be in IFM2 |
| 301 | return False |
| 302 | elif ifm2_shape == []: |
| 303 | return True |
| 304 | |
| 305 | for ifm, ifm2 in zip(ifm_shape, ifm2_shape): |
| 306 | if ifm != ifm2 and ifm == 1: |
| 307 | # Broadcasted FM needs to be in IFM2 |
| 308 | return False |
| 309 | |
| 310 | return True |
| 311 | |
| 312 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 313 | def generate_register_command_stream(nng, sg, arch, verbose=False): |
| 314 | emit = CommandStreamEmitter() |
| 315 | |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 316 | if arch.feature_map_storage_mem_area == arch.fast_storage_mem_area: |
| 317 | base_ptr_idx_map = { |
| 318 | MemType.Permanent_NPU: BasePointerIndex.WeightTensor, |
| 319 | MemType.Permanent_CPU: BasePointerIndex.WeightTensor, |
| 320 | MemType.Scratch: BasePointerIndex.ScratchTensor, |
| 321 | MemType.Scratch_fast: BasePointerIndex.ScratchTensor, |
| 322 | } |
| 323 | else: |
| 324 | base_ptr_idx_map = { |
| 325 | MemType.Permanent_NPU: BasePointerIndex.WeightTensor, |
| 326 | MemType.Permanent_CPU: BasePointerIndex.WeightTensor, |
| 327 | MemType.Scratch: BasePointerIndex.ScratchTensor, |
| 328 | MemType.Scratch_fast: BasePointerIndex.ScratchFastTensor, |
| 329 | } |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 330 | |
| 331 | # Maps an AccumulatorType enum to the corresponding acc_format value |
| 332 | acc_format_map = { |
| 333 | SHRAMElements.Acc16: acc_format.FP_S5_10.value, |
| 334 | SHRAMElements.Acc32: acc_format.INT_32BIT.value, |
| 335 | SHRAMElements.Acc40: acc_format.INT_40BIT.value, |
| 336 | } |
| 337 | |
| 338 | # Maps an elementwise op type to an elementwise_mode enum value used by NPU_OP_ELEMENTWISE |
| 339 | elementwise_mode_map = { |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 340 | Op.Mul: elementwise_mode.MUL.value, |
| 341 | Op.Add: elementwise_mode.ADD.value, |
| 342 | Op.Sub: elementwise_mode.SUB.value, |
| 343 | Op.Minimum: elementwise_mode.MIN.value, |
| 344 | Op.Maximum: elementwise_mode.MAX.value, |
| 345 | Op.LeakyRelu: elementwise_mode.LRELU.value, |
| 346 | Op.Abs: elementwise_mode.ABS.value, |
| 347 | Op.CLZ: elementwise_mode.CLZ.value, |
| 348 | Op.SHR: elementwise_mode.SHR.value, |
| 349 | Op.SHL: elementwise_mode.SHL.value, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | cmd_stream = [] |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 353 | memory_accesses = {} |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 354 | for cmd in sg.high_level_command_stream: |
| 355 | if cmd.cmdtype == CommandType.NpuStripe and cmd.ps.npu_block_type == NpuBlockType.Default: |
| 356 | print("Warning: Skipping register command stream generation for", cmd.ps) |
| 357 | else: |
| 358 | cmd_stream.append(cmd) |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 359 | memory_accesses[cmd] = cmd.get_memory_accesses() |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 360 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 361 | def emit_cmd_waits(cmd_waits): |
| 362 | if cmd_waits.npu >= 0: |
| 363 | emit.cmd_wait(cmd0.NPU_OP_KERNEL_WAIT, 0, cmd_waits.npu) |
| 364 | |
| 365 | if cmd_waits.dma >= 0: |
| 366 | emit.cmd_wait(cmd0.NPU_OP_DMA_WAIT, 0, cmd_waits.dma) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 367 | |
| 368 | # Initialise operator dependency state |
| 369 | prev_ifm_rect = cur_ifm_rect = None |
| 370 | prev_ifm_block_depth = cur_ifm_block_depth = None |
| 371 | prev_ofm_rect = cur_ofm_rect = None |
| 372 | prev_ofm_block = cur_ofm_block = None |
| 373 | prev_kernel = cur_kernel = None |
| 374 | prev_cmd = None |
| 375 | |
Tim Hall | 42e4189 | 2020-07-06 10:51:31 +0100 | [diff] [blame] | 376 | if arch.is_yoda_system: |
Jacob Bohlin | 0b9ca78 | 2020-07-09 11:16:30 +0200 | [diff] [blame] | 377 | emit.cmd0_with_param(cmd0.NPU_SET_PARALLEL_MODE, arch.ncores - 1) |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 378 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 379 | dep_watermark = Watermark(0, 0) |
| 380 | |
| 381 | for cmd_index, cmd in enumerate(cmd_stream): |
| 382 | dep_watermark, cmd_waits = get_cmd_wait_dependency(arch, cmd_stream, memory_accesses, cmd_index, dep_watermark) |
| 383 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 384 | if cmd.cmdtype == CommandType.DMA: |
| 385 | start_coord = cmd.box.start_coord |
| 386 | |
| 387 | src_addr = cmd.in_tensor.address_for_coordinate(start_coord) |
| 388 | dst_addr = cmd.out_tensor.address_for_coordinate(start_coord) |
| 389 | |
| 390 | if cmd.in_tensor.compressed_values is not None: |
| 391 | stream_index = cmd.in_tensor.compressed_stream_index_from_coord(start_coord) |
| 392 | sz = cmd.in_tensor.size_of_compressed_stream(stream_index) |
| 393 | else: |
| 394 | sz = cmd.in_tensor.address_for_coordinate(cmd.box.end_coord, is_top_box=True) - src_addr |
| 395 | |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 396 | emit.cmd0_with_param(cmd0.NPU_SET_DMA0_SRC_REGION, base_ptr_idx_map[cmd.in_tensor.mem_type]) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 397 | emit.cmd1_with_offset(cmd1.NPU_SET_DMA0_SRC, src_addr) |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 398 | if cmd.out_tensor.purpose == TensorPurpose.LUT: |
| 399 | emit.cmd0_with_param(cmd0.NPU_SET_DMA0_DST_REGION, BasePointerIndex.Mem2Mem) |
| 400 | else: |
| 401 | emit.cmd0_with_param(cmd0.NPU_SET_DMA0_DST_REGION, base_ptr_idx_map[cmd.out_tensor.mem_type]) |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 402 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 403 | emit.cmd1_with_offset(cmd1.NPU_SET_DMA0_DST, dst_addr) |
| 404 | emit.cmd1_with_offset(cmd1.NPU_SET_DMA0_LEN, sz) |
| 405 | dma_channel = 0 |
| 406 | mode = 0 # From external to external |
| 407 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 408 | emit_cmd_waits(cmd_waits) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 409 | emit.cmd_do_operation(cmd0.NPU_OP_DMA_START, dma_channel * 16 + mode) |
| 410 | |
| 411 | elif cmd.cmdtype == CommandType.NpuStripe: |
| 412 | |
| 413 | ps = cmd.ps |
| 414 | primary_op = ps.primary_op |
| 415 | npu_block_type = ps.npu_block_type |
| 416 | # Specifies if global scale from the NPU_SET_OFM_SCALE register should be used instead of per-channel scale |
| 417 | use_global_scale = False |
| 418 | # Specifies type of rounding to be used. |
Tim Hall | d775e37 | 2020-08-28 18:33:38 +0100 | [diff] [blame] | 419 | rounding_mode = ( |
| 420 | rounding.NATURAL if primary_op.attrs.get("rounding_mode", "") == b"NATURAL" else rounding.TFL |
| 421 | ) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 422 | if primary_op.type == Op.ResizeBilinear: |
Dwight Lidman | 3ec04ac | 2020-04-30 11:54:48 +0200 | [diff] [blame] | 423 | rounding_mode = rounding.TRUNCATE |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 424 | fmf = primary_op.memory_function |
| 425 | faf = primary_op.activation |
| 426 | fused_quantize = any(op.type == Op.Quantize for op in ps.ops) |
Louis Verhaard | d7911c4 | 2020-08-25 13:36:41 +0200 | [diff] [blame] | 427 | # Force output scale, used in operations with fused LUT |
| 428 | # Note: with current LUT support, forced_ofm_quantization is always equal to cmd.ofm_tensor.quantization |
| 429 | # except when primary_op is AddAct + 0 (no-op) + LUT |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 430 | forced_ofm_quantization = primary_op.forced_output_quantization |
Louis Verhaard | d7911c4 | 2020-08-25 13:36:41 +0200 | [diff] [blame] | 431 | ofm_quant = cmd.ofm_tensor.quantization |
| 432 | if forced_ofm_quantization is not None: |
| 433 | ofm_quant = forced_ofm_quantization |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 434 | |
| 435 | # Specifies which operand to apply scaling to in bitexact elementwise ADD/SUB |
| 436 | op_to_scale = 0 |
| 437 | |
| 438 | # Update state history |
| 439 | prev_ifm_rect = cur_ifm_rect |
| 440 | prev_ifm_block_depth = cur_ifm_block_depth |
| 441 | prev_ofm_rect = cur_ofm_rect |
| 442 | prev_ofm_block = cur_ofm_block |
| 443 | prev_kernel = cur_kernel |
Tim Hall | 4ed38bc | 2020-10-20 18:54:20 +0100 | [diff] [blame] | 444 | cur_kernel = ps.primary_op.kernel if ps.primary_op else None |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 445 | |
| 446 | block_config = ps.block_config |
| 447 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_BLK_HEIGHT_M1, block_config[0] - 1) |
| 448 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_BLK_WIDTH_M1, block_config[1] - 1) |
| 449 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_BLK_DEPTH_M1, block_config[3] - 1) |
| 450 | |
| 451 | shared_buffer = ps.shared_buffer |
| 452 | |
| 453 | if npu_block_type == NpuBlockType.ElementWise: |
Jacob Bohlin | be733cf | 2020-08-13 10:21:34 +0200 | [diff] [blame] | 454 | ifm2_broadcast = 0 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 455 | |
Jacob Bohlin | bf61268 | 2020-08-13 09:37:02 +0200 | [diff] [blame] | 456 | if cmd.ifm2_tensor and not ifm_ifm2_correct_order(cmd.ifm_tensor.shape, cmd.ifm2_tensor.shape): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 457 | # The scalar has to be the ifm2 tensor so switch the ifms |
| 458 | cmd.ifm_tensor, cmd.ifm2_tensor = cmd.ifm2_tensor, cmd.ifm_tensor |
| 459 | cmd.ifm_box, cmd.ifm2_box = cmd.ifm2_box, cmd.ifm_box |
| 460 | |
| 461 | # Set ReverseOperandOrder bit to IFM2_BROADCAST |
| 462 | ifm2_broadcast |= IFM2Broadcast.ReverseOperandOrder |
| 463 | |
| 464 | # Calculate scales needed for arithmetic elementwise operators |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 465 | if primary_op.type in set((Op.Add, Op.Mul, Op.Sub,)): |
Fredrik Svedberg | 0f98b36 | 2020-09-29 10:00:39 +0200 | [diff] [blame] | 466 | input_scale = cmd.ifm_tensor.quantization.scale_f32 if cmd.ifm_tensor.quantization else None |
| 467 | input2_scale = cmd.ifm2_tensor.quantization.scale_f32 if cmd.ifm2_tensor.quantization else None |
| 468 | output_scale = ofm_quant.scale_f32 if ofm_quant else None |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 469 | use_global_scale = True |
| 470 | |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 471 | if output_scale is not None and faf in (Op.Sigmoid, Op.Tanh): |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 472 | output_scale = 1 / 0x3000 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 473 | |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 474 | if primary_op.type == Op.Mul: |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 475 | if None in (input_scale, input2_scale, output_scale): |
| 476 | ofm_scale = 1 |
| 477 | shift = 0 |
| 478 | else: |
| 479 | ofm_scale, shift = scaling.elementwise_mul_scale(input_scale, input2_scale, output_scale) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 480 | emit.cmd1_with_offset(cmd1.NPU_SET_OFM_SCALE, ofm_scale, shift) |
| 481 | else: # AddAct/SubAct |
Charles Xu | 9a03fdf | 2020-07-02 15:12:40 +0200 | [diff] [blame] | 482 | # Force output scale same as the input scale for |
Louis Verhaard | d7911c4 | 2020-08-25 13:36:41 +0200 | [diff] [blame] | 483 | # resizebilinear 1x1 that is converted to add |
Charles Xu | 9a03fdf | 2020-07-02 15:12:40 +0200 | [diff] [blame] | 484 | if "resizebilinear" in primary_op.attrs: |
| 485 | output_scale = input2_scale |
| 486 | |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 487 | if None in (input_scale, input2_scale, output_scale): |
| 488 | opa_scale = opb_scale = ofm_scale = 1 |
| 489 | opa_shift = shift = 0 |
Fredrik Svedberg | 597fd3f | 2020-08-13 10:02:53 +0200 | [diff] [blame] | 490 | ofm_scale, shift = primary_op.attrs.get("rescale", [1, 0]) |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 491 | elif input_scale == input2_scale: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 492 | opa_scale, opb_scale, ofm_scale, shift = scaling.simplified_elementwise_add_sub_scale( |
| 493 | input_scale, input2_scale, output_scale |
| 494 | ) |
| 495 | opa_shift = 0 # Unused for this case |
| 496 | else: |
| 497 | # Use advanced implementation only when input scales differ |
| 498 | bitdepth = cmd.ifm_tensor.dtype.bits |
| 499 | ( |
| 500 | opa_scale, |
| 501 | opa_shift, |
| 502 | ofm_scale, |
| 503 | shift, |
| 504 | op_to_scale, |
| 505 | ) = scaling.advanced_elementwise_add_sub_scale( |
| 506 | input_scale, input2_scale, output_scale, bitdepth |
| 507 | ) |
| 508 | opb_scale = 0 # Unused for this case |
| 509 | if ifm2_broadcast & IFM2Broadcast.ReverseOperandOrder: |
| 510 | # If the operand order is reversed we also have to swap which operand is scaled |
| 511 | if op_to_scale == scaling.OperandToScale.OPa: |
| 512 | op_to_scale = scaling.OperandToScale.OPb |
| 513 | else: |
| 514 | op_to_scale = scaling.OperandToScale.OPa |
| 515 | |
| 516 | emit.cmd1_with_offset(cmd1.NPU_SET_OPA_SCALE, opa_scale, opa_shift) |
| 517 | emit.cmd1_with_offset(cmd1.NPU_SET_OPB_SCALE, opb_scale) |
| 518 | emit.cmd1_with_offset(cmd1.NPU_SET_OFM_SCALE, ofm_scale, shift) |
| 519 | |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 520 | elif primary_op.type in set((Op.LeakyRelu, Op.Abs,)): |
Louis Verhaard | d7911c4 | 2020-08-25 13:36:41 +0200 | [diff] [blame] | 521 | output_scale = ofm_quant.scale_f32 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 522 | use_global_scale = True |
| 523 | |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 524 | if primary_op.type == Op.LeakyRelu: |
Louis Verhaard | 58520b9 | 2020-08-24 16:45:38 +0200 | [diff] [blame] | 525 | output_scale = primary_op.attrs["alpha"] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 526 | |
| 527 | ofm_scale, shift = scaling.quantise_scale(output_scale) |
| 528 | emit.cmd1_with_offset(cmd1.NPU_SET_OFM_SCALE, ofm_scale, shift) |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 529 | else: |
| 530 | emit.cmd1_with_offset(cmd1.NPU_SET_OFM_SCALE, 1, 0) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 531 | |
Louis Verhaard | 0b8268a | 2020-08-05 16:11:29 +0200 | [diff] [blame] | 532 | # For elementwise set the required SHRAM to be equal to the total size of available SHRAM |
| 533 | uses_lut = primary_op.activation_lut is not None |
| 534 | shram_required = arch.available_shram_banks(uses_lut) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 535 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_IB_END, shram_required) |
| 536 | |
| 537 | # Acc buffers not needed so set AB_START to size of SHRAM |
Louis Verhaard | 0b8268a | 2020-08-05 16:11:29 +0200 | [diff] [blame] | 538 | emit.cmd0_with_param(cmd0.NPU_SET_AB_START, shram_required) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 539 | |
| 540 | # Is not a unary operator |
| 541 | if cmd.ifm2_tensor is not None: |
| 542 | if cmd.ifm2_tensor.shape == []: |
| 543 | # IFM2 is a constant, set UseIFM2Scalar bit to IFM2_BROADCAST |
| 544 | ifm2_broadcast |= IFM2Broadcast.UseIFM2Scalar |
| 545 | else: |
| 546 | ifm_box_shape = cmd.ifm_box.get_size_shape() |
| 547 | ifm2_box_shape = cmd.ifm2_box.get_size_shape() |
| 548 | |
| 549 | if len(cmd.ifm_tensor.shape) > 1 and ifm_box_shape[1] != ifm2_box_shape[1]: |
| 550 | # Broadcast in 'H' dimension |
| 551 | assert cmd.ifm2_tensor.shape[1] == 1 |
| 552 | ifm2_broadcast |= IFM2Broadcast.BroadcastHdim |
| 553 | |
| 554 | if len(cmd.ifm_tensor.shape) > 2 and ifm_box_shape[2] != ifm2_box_shape[2]: |
| 555 | # Broadcast in 'W' dimension |
| 556 | assert cmd.ifm2_tensor.shape[2] == 1 |
| 557 | ifm2_broadcast |= IFM2Broadcast.BroadcastWdim |
| 558 | |
| 559 | if len(cmd.ifm_tensor.shape) > 3 and ifm_box_shape[3] != ifm2_box_shape[3]: |
| 560 | # Broadcast in 'C' dimension |
| 561 | assert cmd.ifm2_tensor.shape[3] == 1 |
| 562 | ifm2_broadcast |= IFM2Broadcast.BroadcastCdim |
| 563 | |
| 564 | # Set IFM2_IB_START to the latter half of the IB space |
| 565 | ifm_ib_start = shared_buffer.bank_locations[SharedBufferArea.IFM] |
| 566 | emit.cmd0_with_param( |
Tim Hall | 4ed38bc | 2020-10-20 18:54:20 +0100 | [diff] [blame] | 567 | cmd0.NPU_SET_IFM2_IB_START, |
| 568 | (shram_required - ifm_ib_start) // shared_buffer.ifm_count + ifm_ib_start, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 569 | ) |
| 570 | |
| 571 | emit.cmd0_with_param(cmd0.NPU_SET_IFM2_BROADCAST, ifm2_broadcast) |
| 572 | |
| 573 | else: |
| 574 | emit.cmd0_with_param( |
| 575 | cmd0.NPU_SET_IFM_IB_END, |
| 576 | shared_buffer.bank_locations[SharedBufferArea.IFM] |
| 577 | + shared_buffer.banks_required[SharedBufferArea.IFM], |
| 578 | ) |
| 579 | emit.cmd0_with_param(cmd0.NPU_SET_AB_START, shared_buffer.bank_locations[SharedBufferArea.Accumulators]) |
| 580 | |
| 581 | emit.cmd0_with_param(cmd0.NPU_SET_ACC_FORMAT, acc_format_map[shared_buffer.use_accumulator_element]) |
| 582 | |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 583 | if primary_op.type == Op.ResizeBilinear: |
Dwight Lidman | 3ec04ac | 2020-04-30 11:54:48 +0200 | [diff] [blame] | 584 | # perform nearest neighbor upscale |
Jacob Bohlin | cf7da10 | 2020-05-20 09:03:40 +0200 | [diff] [blame] | 585 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_UPSCALE, resampling_mode.NEAREST) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 586 | elif primary_op.type == Op.Conv2DBackpropInputSwitchedBias: |
Jacob Bohlin | cf7da10 | 2020-05-20 09:03:40 +0200 | [diff] [blame] | 587 | # perform insert zero upscale |
| 588 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_UPSCALE, resampling_mode.TRANSPOSE) |
Dwight Lidman | 3ec04ac | 2020-04-30 11:54:48 +0200 | [diff] [blame] | 589 | else: |
Jacob Bohlin | cf7da10 | 2020-05-20 09:03:40 +0200 | [diff] [blame] | 590 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_UPSCALE, resampling_mode.NONE) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 591 | |
| 592 | if npu_block_type in set( |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 593 | ( |
| 594 | NpuBlockType.ConvolutionMxN, |
| 595 | NpuBlockType.ConvolutionDepthWise, |
| 596 | NpuBlockType.Pooling, |
| 597 | NpuBlockType.ReduceSum, |
| 598 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 599 | ): |
| 600 | # Set up padding |
| 601 | explicit_padding = list(primary_op.attrs["explicit_padding"]) # (top, left, bottom, right) |
| 602 | |
| 603 | # Check if this is for horizontal ifm streaming |
| 604 | if not (cmd.is_first_h_stripe and cmd.is_last_h_stripe): |
| 605 | explicit_padding[0] = cmd.pad_top |
| 606 | explicit_padding[2] = cmd.pad_bottom |
| 607 | |
| 608 | # Indexing from end since a 1x1 Avgpool might have been added with non 4-dimensional input/output, |
| 609 | # because of activation function needed to be fused. |
| 610 | if cmd.ifm_box.start_coord[-2] > 0: |
| 611 | explicit_padding[1] = 0 |
| 612 | if cmd.ifm_box.end_coord[-2] < cmd.ifm_tensor.shape[-2]: |
| 613 | explicit_padding[3] = 0 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 614 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PAD_TOP, explicit_padding[0]) |
| 615 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PAD_LEFT, explicit_padding[1]) |
| 616 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PAD_BOTTOM, explicit_padding[2]) |
| 617 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PAD_RIGHT, explicit_padding[3]) |
| 618 | |
Dwight Lidman | 0538a77 | 2020-05-06 14:09:17 +0200 | [diff] [blame] | 619 | # set kernel x stride low bit |
| 620 | stride = primary_op.attrs["strides"][2] - 1 & 1 |
| 621 | # set kernel y stride low bit |
| 622 | stride |= (primary_op.attrs["strides"][1] - 1 & 1) << 1 |
| 623 | # set kernel x stride extension bits |
| 624 | stride |= (primary_op.attrs["strides"][2] - 1 >> 1) << 6 |
| 625 | # set kernel y stride extension bits |
| 626 | stride |= (primary_op.attrs["strides"][1] - 1 >> 1) << 9 |
| 627 | |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 628 | if npu_block_type in set((NpuBlockType.Pooling, NpuBlockType.ReduceSum)): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 629 | k_height, k_width = primary_op.attrs["ksize"][1:3] |
| 630 | emit.cmd0_with_param(cmd0.NPU_SET_KERNEL_HEIGHT_M1, k_height - 1) |
| 631 | emit.cmd0_with_param(cmd0.NPU_SET_KERNEL_WIDTH_M1, k_width - 1) |
| 632 | |
| 633 | valid_padding = sum(explicit_padding) == 0 |
| 634 | |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 635 | if primary_op.type in set((Op.AvgPool, Op.ResizeBilinear, Op.ReduceSum)) and valid_padding: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 636 | # For valid padding vela has to output scaling values |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 637 | if faf == Op.Sigmoid or faf == Op.Tanh: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 638 | rescale = 0x3000 * cmd.ifm_tensor.quantization.scale_f32 |
Fredrik Svedberg | 620d88c | 2020-05-19 10:43:01 +0200 | [diff] [blame] | 639 | if cmd.ifm_tensor.dtype == DataType.int16: |
Charles Xu | f899231 | 2020-08-18 08:41:54 +0200 | [diff] [blame] | 640 | # Calculate scale and shift for the output scale of 1/(3*4096) |
| 641 | shift = 0 |
| 642 | max_rescale = np.iinfo(np.int16).max / 2 |
| 643 | while rescale <= max_rescale and shift <= 30: |
| 644 | shift += 1 |
| 645 | rescale *= 2 |
| 646 | scale = int(rescale) |
Fredrik Svedberg | 620d88c | 2020-05-19 10:43:01 +0200 | [diff] [blame] | 647 | else: |
Charles Xu | f899231 | 2020-08-18 08:41:54 +0200 | [diff] [blame] | 648 | rescale_bits = len(bin(round_up_to_int(rescale))) - 2 + 1 |
| 649 | scale, shift = scaling.quantise_pooling_scale(k_height * k_width, rescale_bits) |
Fredrik Svedberg | 620d88c | 2020-05-19 10:43:01 +0200 | [diff] [blame] | 650 | scale = int(round_away_zero(scale * rescale)) |
Jacob Bohlin | 9fbc491 | 2020-06-29 11:58:50 +0200 | [diff] [blame] | 651 | elif fused_quantize: |
| 652 | # Quantize op requires different scaling |
| 653 | ifm_scale_f64 = np.double(cmd.ifm_tensor.quantization.scale_f32) |
Louis Verhaard | d7911c4 | 2020-08-25 13:36:41 +0200 | [diff] [blame] | 654 | ofm_scale_f64 = np.double(ofm_quant.scale_f32) |
Jacob Bohlin | 9fbc491 | 2020-06-29 11:58:50 +0200 | [diff] [blame] | 655 | scale, shift = scaling.quantise_scale(ifm_scale_f64 / ofm_scale_f64) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 656 | elif primary_op.type == Op.ResizeBilinear and "rescale" in primary_op.attrs: |
Charles Xu | 87c1350 | 2020-08-06 12:17:26 +0200 | [diff] [blame] | 657 | rescale = primary_op.attrs["rescale"] |
| 658 | rescale_bits = len(bin(round_up_to_int(rescale))) - 2 + 1 |
| 659 | scale, shift = scaling.quantise_pooling_scale(k_height * k_width, rescale_bits) |
| 660 | scale = int(round_away_zero(scale * rescale)) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 661 | else: |
| 662 | # In case avg pool fused with concat or other memory operation, rescaling might be needed. |
| 663 | # k_height == k_width == 1 is allways true in this case |
| 664 | # Normally the scale is maximised, to get maximum precision, which means that |
| 665 | # if rescale != 1, scale need to consider the number of bits needed for rescaling |
Louis Verhaard | d7911c4 | 2020-08-25 13:36:41 +0200 | [diff] [blame] | 666 | if None not in (ofm_quant.scale_f32, cmd.ifm_tensor.quantization.scale_f32,): |
| 667 | rescale = cmd.ifm_tensor.quantization.scale_f32 / ofm_quant.scale_f32 |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 668 | rescale_bits = 0 |
| 669 | if k_height == k_width == 1: |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 670 | if fmf == Op.ConcatSliceWrite: |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 671 | rounding_mode = rounding.NATURAL |
| 672 | if rescale > 1: |
| 673 | rescale_bits = len(bin(round_up_to_int(rescale))) - 2 + 1 |
| 674 | elif rescale < 1: |
| 675 | rescale_bits = -(len(bin(round_up_to_int(1 / rescale))) - 2 - 1) |
| 676 | scale, shift = scaling.quantise_pooling_scale(k_height * k_width, rescale_bits) |
| 677 | scale = int(round_away_zero(scale * rescale)) |
| 678 | else: |
| 679 | scale = 1 |
| 680 | shift = 0 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 681 | |
| 682 | emit.cmd1_with_offset(cmd1.NPU_SET_OFM_SCALE, scale, shift) |
| 683 | # Valid-padded average pool should use the global scale from |
| 684 | # NPU_SET_OFM_SCALE register, which is set above. |
| 685 | use_global_scale = True |
| 686 | |
| 687 | else: # Convolution |
| 688 | assert cmd.weight_tensor.block_traversal != TensorBlockTraversal.Default |
Fredrik Svedberg | d67c0aa | 2020-03-30 13:15:28 +0200 | [diff] [blame] | 689 | # Reduced precision quantization and natural rounding used for int16 |
| 690 | if cmd.ifm_tensor.dtype == DataType.int16: |
| 691 | rounding_mode = rounding.NATURAL |
Louis Verhaard | b2fb212 | 2020-06-04 15:51:24 +0200 | [diff] [blame] | 692 | stride |= (cur_kernel.dilation.y - 1) << 4 |
| 693 | stride |= (cur_kernel.dilation.x - 1) << 3 |
| 694 | emit.cmd0_with_param( |
| 695 | cmd0.NPU_SET_KERNEL_HEIGHT_M1, cur_kernel.dilation.y * (cmd.weight_tensor.shape[0] - 1) |
| 696 | ) |
| 697 | emit.cmd0_with_param( |
| 698 | cmd0.NPU_SET_KERNEL_WIDTH_M1, cur_kernel.dilation.x * (cmd.weight_tensor.shape[1] - 1) |
| 699 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 700 | if cmd.weight_tensor.block_traversal == TensorBlockTraversal.PartKernelFirst: |
| 701 | # Part-kernel-first weight ordering |
| 702 | assert npu_block_type == NpuBlockType.ConvolutionMxN |
| 703 | stride |= 1 << 2 |
| 704 | |
| 705 | emit.cmd0_with_param(cmd0.NPU_SET_KERNEL_STRIDE, stride) |
| 706 | |
| 707 | elif npu_block_type in set((NpuBlockType.VectorProduct,)): |
| 708 | # Vector product is implemented using a 1x1 convolution so need |
| 709 | # to setup the appropriate padding and kernel info |
| 710 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PAD_TOP, 0) |
| 711 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PAD_LEFT, 0) |
| 712 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PAD_BOTTOM, 0) |
| 713 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PAD_RIGHT, 0) |
| 714 | |
| 715 | # kernel stride reg = 0 means stride(1,1) + depth first weight |
| 716 | # order + dilation(0,0) + kernel_split_size=8 |
| 717 | emit.cmd0_with_param(cmd0.NPU_SET_KERNEL_STRIDE, 0) |
| 718 | |
| 719 | emit.cmd0_with_param(cmd0.NPU_SET_KERNEL_HEIGHT_M1, 0) |
| 720 | emit.cmd0_with_param(cmd0.NPU_SET_KERNEL_WIDTH_M1, 0) |
| 721 | |
| 722 | if npu_block_type in set( |
| 723 | (NpuBlockType.ConvolutionMxN, NpuBlockType.ConvolutionDepthWise, NpuBlockType.VectorProduct) |
| 724 | ): |
| 725 | # Emit Weight base address commands, only maps the area required for |
| 726 | # this command's weights from the larger tensor. |
| 727 | stream_index = cmd.weight_tensor.compressed_stream_index_from_coord(cmd.weight_box.start_coord) |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 728 | weight_substream_offsets = cmd.weight_tensor.compressed_values_substream_offsets[stream_index] |
Jacob Bohlin | 0b9ca78 | 2020-07-09 11:16:30 +0200 | [diff] [blame] | 729 | substreams = len(weight_substream_offsets) - 1 # Offset list must terminate with full stream length |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 730 | |
| 731 | # Extract weight substream offsets and calculate their lengths |
| 732 | assert len(weight_substream_offsets) > 1 and (weight_substream_offsets[0] == 0) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 733 | weight_addr = cmd.weight_tensor.address_for_coordinate(cmd.weight_box.start_coord) |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 734 | |
Tim Hall | 6231676 | 2020-06-25 16:55:02 +0100 | [diff] [blame] | 735 | # Set weights sources for active and present cores |
Jacob Bohlin | 0b9ca78 | 2020-07-09 11:16:30 +0200 | [diff] [blame] | 736 | for core, param in enumerate( |
| 737 | [ |
| 738 | (cmd1.NPU_SET_WEIGHT_BASE, cmd1.NPU_SET_WEIGHT_LENGTH), |
| 739 | (cmd1.NPU_SET_WEIGHT1_BASE, cmd1.NPU_SET_WEIGHT1_LENGTH), |
| 740 | ] |
| 741 | ): |
Tim Hall | 6231676 | 2020-06-25 16:55:02 +0100 | [diff] [blame] | 742 | if core < substreams: |
Jacob Bohlin | 0b9ca78 | 2020-07-09 11:16:30 +0200 | [diff] [blame] | 743 | emit.cmd1_with_offset(param[0], weight_addr + weight_substream_offsets[core]) |
| 744 | emit.cmd1_with_offset( |
| 745 | param[1], weight_substream_offsets[core + 1] - weight_substream_offsets[core] |
| 746 | ) |
Tim Hall | 6231676 | 2020-06-25 16:55:02 +0100 | [diff] [blame] | 747 | elif core < arch.ncores: |
| 748 | emit.cmd1_with_offset(param[0], weight_addr) |
| 749 | emit.cmd1_with_offset(param[1], 0) |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 750 | |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 751 | weight_region = base_ptr_idx_map[cmd.weight_tensor.mem_type] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 752 | emit.cmd0_with_param(cmd0.NPU_SET_WEIGHT_REGION, weight_region) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 753 | |
| 754 | # Emit Scale & Bias base address commands, with length matching the amount required by |
| 755 | # the weight tensors. |
| 756 | if cmd.scale_tensor is not None: |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 757 | scale_substream_offsets = cmd.scale_tensor.compressed_values_substream_offsets[stream_index] |
Jacob Bohlin | 0b9ca78 | 2020-07-09 11:16:30 +0200 | [diff] [blame] | 758 | substreams = len(scale_substream_offsets) - 1 # Offset list must terminate with full stream length |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 759 | |
| 760 | # Extract scale substream offsets and calculate their lengths |
| 761 | assert len(scale_substream_offsets) > 1 and (scale_substream_offsets[0] == 0) |
Jacob Bohlin | 0b9ca78 | 2020-07-09 11:16:30 +0200 | [diff] [blame] | 762 | scale_addr = cmd.scale_tensor.address_for_coordinate(cmd.weight_box.start_coord[-1:]) |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 763 | |
Tim Hall | 6231676 | 2020-06-25 16:55:02 +0100 | [diff] [blame] | 764 | # Set scale sources for active and present cores |
Jacob Bohlin | 0b9ca78 | 2020-07-09 11:16:30 +0200 | [diff] [blame] | 765 | for core, param in enumerate( |
| 766 | [ |
| 767 | (cmd1.NPU_SET_SCALE_BASE, cmd1.NPU_SET_SCALE_LENGTH), |
| 768 | (cmd1.NPU_SET_SCALE1_BASE, cmd1.NPU_SET_SCALE1_LENGTH), |
| 769 | ] |
| 770 | ): |
Tim Hall | 6231676 | 2020-06-25 16:55:02 +0100 | [diff] [blame] | 771 | if core < substreams: |
Jacob Bohlin | 0b9ca78 | 2020-07-09 11:16:30 +0200 | [diff] [blame] | 772 | emit.cmd1_with_offset(param[0], scale_addr + scale_substream_offsets[core]) |
| 773 | emit.cmd1_with_offset( |
| 774 | param[1], scale_substream_offsets[core + 1] - scale_substream_offsets[core] |
| 775 | ) |
Tim Hall | 6231676 | 2020-06-25 16:55:02 +0100 | [diff] [blame] | 776 | elif core < arch.ncores: |
| 777 | emit.cmd1_with_offset(param[0], scale_addr) |
| 778 | emit.cmd1_with_offset(param[1], 0) |
Tim Hall | f7e810a | 2020-06-25 15:04:31 +0100 | [diff] [blame] | 779 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 780 | # Emit base address for NPU to access scale & bias data |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 781 | scale_region = base_ptr_idx_map[cmd.scale_tensor.mem_type] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 782 | emit.cmd0_with_param(cmd0.NPU_SET_SCALE_REGION, scale_region) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 783 | |
Fredrik Svedberg | 0f98b36 | 2020-09-29 10:00:39 +0200 | [diff] [blame] | 784 | ofm_quant_qmin = ofm_quant.quant_min if ofm_quant else np.iinfo(np.int16).min |
| 785 | ofm_quant_qmax = ofm_quant.quant_max if ofm_quant else np.iinfo(np.int16).max |
| 786 | ifm_min = cmd.ifm_tensor.quantization.min if cmd.ifm_tensor.quantization else np.iinfo(np.int16).min |
| 787 | ifm_max = cmd.ifm_tensor.quantization.max if cmd.ifm_tensor.quantization else np.iinfo(np.int16).max |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 788 | |
| 789 | # Emit commands for any fused activation function |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 790 | if faf is None: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 791 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION, activation.NONE) |
| 792 | # Even if no activation function, values need to be set to override previous values |
| 793 | faf_min = ofm_quant_qmin |
| 794 | faf_max = ofm_quant_qmax |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 795 | elif faf == Op.Relu: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 796 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION, activation.NONE) |
| 797 | faf_min = quantise_float32(0.0, ofm_quant.scale_f32, ofm_quant.zero_point) |
| 798 | faf_max = ofm_quant_qmax |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 799 | elif faf == Op.Relu6: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 800 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION, activation.NONE) |
| 801 | faf_min = quantise_float32(0.0, ofm_quant.scale_f32, ofm_quant.zero_point) |
| 802 | faf_max = quantise_float32(6.0, ofm_quant.scale_f32, ofm_quant.zero_point) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 803 | elif faf == Op.ReluN1To1: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 804 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION, activation.NONE) |
| 805 | faf_min = quantise_float32(-1.0, ofm_quant.scale_f32, ofm_quant.zero_point) |
| 806 | faf_max = quantise_float32(1.0, ofm_quant.scale_f32, ofm_quant.zero_point) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 807 | elif faf == Op.Tanh: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 808 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION, activation.TANH) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 809 | if primary_op.type in set((Op.AvgPool, Op.ResizeBilinear)): |
Fredrik Svedberg | 620d88c | 2020-05-19 10:43:01 +0200 | [diff] [blame] | 810 | faf_min = quantise_float32(-1.0, ofm_quant.scale_f32, ofm_quant.zero_point) |
| 811 | faf_max = quantise_float32(1.0, ofm_quant.scale_f32, ofm_quant.zero_point) |
| 812 | else: |
| 813 | faf_min = quantise_float32(clamp_tanh(ifm_min), ofm_quant.scale_f32, ofm_quant.zero_point) |
| 814 | faf_max = quantise_float32(clamp_tanh(ifm_max), ofm_quant.scale_f32, ofm_quant.zero_point) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 815 | elif faf == Op.Sigmoid: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 816 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION, activation.SIGMOID) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 817 | if primary_op.type in set((Op.AvgPool, Op.ResizeBilinear)): |
Fredrik Svedberg | 620d88c | 2020-05-19 10:43:01 +0200 | [diff] [blame] | 818 | faf_min = quantise_float32(0, ofm_quant.scale_f32, ofm_quant.zero_point) |
| 819 | faf_max = quantise_float32(1.0, ofm_quant.scale_f32, ofm_quant.zero_point) |
| 820 | else: |
| 821 | faf_min = quantise_float32(clamp_sigmoid(ifm_min), ofm_quant.scale_f32, ofm_quant.zero_point) |
| 822 | faf_max = quantise_float32(clamp_sigmoid(ifm_max), ofm_quant.scale_f32, ofm_quant.zero_point) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 823 | elif faf == Op.LUT: |
Louis Verhaard | 0b8268a | 2020-08-05 16:11:29 +0200 | [diff] [blame] | 824 | lut_index = int(activation.LUT_START.value) + primary_op.attrs.get("lut_index", -1) |
| 825 | assert activation.LUT_START.value <= lut_index <= activation.LUT_END.value, "LUT index out of range." |
Fredrik Svedberg | 597fd3f | 2020-08-13 10:02:53 +0200 | [diff] [blame] | 826 | if cmd.ofm_tensor.dtype == DataType.int32: |
Fredrik Svedberg | 1575b94 | 2020-08-18 13:19:18 +0200 | [diff] [blame] | 827 | lut_index |= 3 << 12 # Force I8 range |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 828 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION, lut_index) |
| 829 | faf_min = ofm_quant_qmin |
| 830 | faf_max = ofm_quant_qmax |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 831 | else: |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 832 | raise Exception("Unsupported fused_activation_function = " + faf.name) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 833 | |
| 834 | # Activation range needs to be set based upon the quantisation range and the fused activation range |
| 835 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION_MIN, max(ofm_quant_qmin, faf_min)) |
| 836 | emit.cmd0_with_param(cmd0.NPU_SET_ACTIVATION_MAX, min(ofm_quant_qmax, faf_max)) |
| 837 | |
| 838 | out_shape = cmd.ofm_box.get_size_shape() |
| 839 | if len(out_shape) >= 4: |
| 840 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_HEIGHT_M1, out_shape[-3] - 1) |
| 841 | else: |
| 842 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_HEIGHT_M1, 0) |
| 843 | if len(out_shape) >= 2: |
| 844 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_WIDTH_M1, out_shape[-2] - 1) |
| 845 | else: |
| 846 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_WIDTH_M1, 0) |
| 847 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_DEPTH_M1, out_shape[-1] - 1) |
| 848 | |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 849 | if npu_block_type in set((NpuBlockType.ConvolutionMxN, NpuBlockType.VectorProduct, NpuBlockType.ReduceSum)): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 850 | in_shape = cmd.ifm_box.get_size_shape() |
| 851 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_DEPTH_M1, in_shape[-1] - 1) |
| 852 | else: |
| 853 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_DEPTH_M1, out_shape[-1] - 1) |
| 854 | |
Jacob Bohlin | 3c67829 | 2020-04-27 10:27:25 +0200 | [diff] [blame] | 855 | for tens, box, region_op, ptr_ops, stride_ops, zero_point_op in ( |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 856 | ( |
| 857 | cmd.ifm_tensor, |
| 858 | cmd.ifm_box, |
Jacob Bohlin | 3c67829 | 2020-04-27 10:27:25 +0200 | [diff] [blame] | 859 | cmd0.NPU_SET_IFM_REGION, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 860 | (cmd1.NPU_SET_IFM_BASE0, cmd1.NPU_SET_IFM_BASE1, cmd1.NPU_SET_IFM_BASE2, cmd1.NPU_SET_IFM_BASE3), |
| 861 | (cmd1.NPU_SET_IFM_STRIDE_C, cmd1.NPU_SET_IFM_STRIDE_Y, cmd1.NPU_SET_IFM_STRIDE_X), |
| 862 | cmd0.NPU_SET_IFM_ZERO_POINT, |
| 863 | ), |
| 864 | ( |
| 865 | cmd.ifm2_tensor, |
| 866 | cmd.ifm2_box, |
Jacob Bohlin | 3c67829 | 2020-04-27 10:27:25 +0200 | [diff] [blame] | 867 | cmd0.NPU_SET_IFM2_REGION, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 868 | ( |
| 869 | cmd1.NPU_SET_IFM2_BASE0, |
| 870 | cmd1.NPU_SET_IFM2_BASE1, |
| 871 | cmd1.NPU_SET_IFM2_BASE2, |
| 872 | cmd1.NPU_SET_IFM2_BASE3, |
| 873 | ), |
| 874 | (cmd1.NPU_SET_IFM2_STRIDE_C, cmd1.NPU_SET_IFM2_STRIDE_Y, cmd1.NPU_SET_IFM2_STRIDE_X), |
| 875 | cmd0.NPU_SET_IFM2_ZERO_POINT, |
| 876 | ), |
| 877 | ( |
| 878 | cmd.ofm_tensor, |
| 879 | cmd.ofm_box, |
Jacob Bohlin | 3c67829 | 2020-04-27 10:27:25 +0200 | [diff] [blame] | 880 | cmd0.NPU_SET_OFM_REGION, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 881 | (cmd1.NPU_SET_OFM_BASE0, cmd1.NPU_SET_OFM_BASE1, cmd1.NPU_SET_OFM_BASE2, cmd1.NPU_SET_OFM_BASE3), |
| 882 | (cmd1.NPU_SET_OFM_STRIDE_C, cmd1.NPU_SET_OFM_STRIDE_Y, cmd1.NPU_SET_OFM_STRIDE_X), |
| 883 | cmd0.NPU_SET_OFM_ZERO_POINT, |
| 884 | ), |
| 885 | ): |
| 886 | |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 887 | if tens is None: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 888 | continue |
| 889 | |
Louis Verhaard | 98a3499 | 2020-09-01 10:39:04 +0200 | [diff] [blame] | 890 | need_zero_point = ( |
| 891 | (faf is not None and forced_ofm_quantization is None) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 892 | or (fmf == Op.ConcatSliceWrite) |
Louis Verhaard | 98a3499 | 2020-09-01 10:39:04 +0200 | [diff] [blame] | 893 | or fused_quantize |
| 894 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 895 | if ( |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 896 | (primary_op.type in set((Op.AvgPool, Op.ResizeBilinear, Op.CLZ, Op.SHL)) and not need_zero_point) |
Fredrik Svedberg | 237d72d | 2020-08-28 18:12:28 +0200 | [diff] [blame] | 897 | or ( |
| 898 | tens.dtype == DataType.int32 |
| 899 | and zero_point_op in (cmd0.NPU_SET_IFM_ZERO_POINT, cmd0.NPU_SET_IFM2_ZERO_POINT) |
| 900 | ) |
| 901 | or tens.quantization is None |
| 902 | ): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 903 | # Actual integer operation, just set scale to 1 and zero point to 0 |
| 904 | emit.cmd0_with_param(zero_point_op, 0) |
| 905 | else: |
| 906 | assert tens.quantization.zero_point is not None, "need an actual zero point set" |
Louis Verhaard | d7911c4 | 2020-08-25 13:36:41 +0200 | [diff] [blame] | 907 | if cmd0.NPU_SET_OFM_ZERO_POINT == zero_point_op and forced_ofm_quantization is not None: |
| 908 | zero_point = forced_ofm_quantization.zero_point |
| 909 | elif ( |
Charles Xu | 9a03fdf | 2020-07-02 15:12:40 +0200 | [diff] [blame] | 910 | "resizebilinear" in primary_op.attrs |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 911 | and primary_op.type == Op.Add |
Charles Xu | 9a03fdf | 2020-07-02 15:12:40 +0200 | [diff] [blame] | 912 | and cmd0.NPU_SET_OFM_ZERO_POINT == zero_point_op |
| 913 | ): |
| 914 | # Force output zero point same as the input zero point |
Louis Verhaard | d7911c4 | 2020-08-25 13:36:41 +0200 | [diff] [blame] | 915 | # for resizebilinear 1x1 that is converted to add |
Charles Xu | 9a03fdf | 2020-07-02 15:12:40 +0200 | [diff] [blame] | 916 | zero_point = cmd.ifm2_tensor.quantization.zero_point |
| 917 | else: |
| 918 | zero_point = tens.quantization.zero_point |
| 919 | emit.cmd0_with_param(zero_point_op, int(zero_point)) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 920 | |
| 921 | if tens.shape == []: |
| 922 | # Empty shape, elementwise constant |
Louis Verhaard | c88a96f | 2020-06-10 09:04:33 +0200 | [diff] [blame] | 923 | ifm2_scalar = tens.quant_values |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 924 | assert ifm2_scalar.size == 1 |
Louis Verhaard | c88a96f | 2020-06-10 09:04:33 +0200 | [diff] [blame] | 925 | emit.cmd0_with_param(cmd0.NPU_SET_IFM2_SCALAR, int(ifm2_scalar.item(0))) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 926 | continue |
| 927 | |
| 928 | height_0, height_1, width_0, addresses = tens.addresses_for_rolling_buffer( |
| 929 | box.start_coord, box.end_coord |
| 930 | ) |
| 931 | if npu_block_type != NpuBlockType.VectorProduct: |
| 932 | if tens == cmd.ifm_tensor: |
| 933 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_HEIGHT0_M1, height_0 - 1) |
| 934 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_HEIGHT1_M1, height_1 - 1) |
| 935 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_WIDTH0_M1, width_0 - 1) |
| 936 | elif tens == cmd.ofm_tensor: |
| 937 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_HEIGHT0_M1, height_0 - 1) |
| 938 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_HEIGHT1_M1, height_1 - 1) |
| 939 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_WIDTH0_M1, width_0 - 1) |
Louis Verhaard | 0cf06c7 | 2020-05-12 08:31:05 +0200 | [diff] [blame] | 940 | if tens == cmd.ifm2_tensor: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 941 | emit.cmd0_with_param(cmd0.NPU_SET_IFM2_HEIGHT0_M1, height_0 - 1) |
| 942 | emit.cmd0_with_param(cmd0.NPU_SET_IFM2_HEIGHT1_M1, height_1 - 1) |
| 943 | emit.cmd0_with_param(cmd0.NPU_SET_IFM2_WIDTH0_M1, width_0 - 1) |
| 944 | else: |
| 945 | if len(out_shape) == 2: |
Patrik Gustavsson | cb33704 | 2020-09-16 14:55:40 +0200 | [diff] [blame] | 946 | assert out_shape[0] == 1 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 947 | if tens == cmd.ifm_tensor: |
Patrik Gustavsson | cb33704 | 2020-09-16 14:55:40 +0200 | [diff] [blame] | 948 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_WIDTH0_M1, 0) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 949 | elif tens == cmd.ofm_tensor: |
Patrik Gustavsson | cb33704 | 2020-09-16 14:55:40 +0200 | [diff] [blame] | 950 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_WIDTH0_M1, 0) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 951 | else: |
| 952 | assert False |
| 953 | |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 954 | emit.cmd0_with_param(region_op, base_ptr_idx_map[tens.mem_type]) |
Jacob Bohlin | 3c67829 | 2020-04-27 10:27:25 +0200 | [diff] [blame] | 955 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 956 | for idx, addr in enumerate(addresses): |
| 957 | if addr is None: |
| 958 | addresses[idx] = 0 |
| 959 | |
| 960 | emit.cmd1_with_offset(ptr_ops[0], addresses[0]) |
| 961 | emit.cmd1_with_offset(ptr_ops[1], addresses[1]) |
| 962 | emit.cmd1_with_offset(ptr_ops[2], addresses[2]) |
| 963 | emit.cmd1_with_offset(ptr_ops[3], addresses[3]) |
| 964 | |
| 965 | strides = tens.get_strides() |
| 966 | emit.cmd1_with_offset(stride_ops[0], strides[1]) # stride between 16-byte channel blocks (C) |
| 967 | emit.cmd1_with_offset(stride_ops[2], strides[3]) # stride between horisontal values (W) |
| 968 | emit.cmd1_with_offset(stride_ops[1], strides[2]) # stride between vertical values (H) |
| 969 | |
| 970 | if tens.format == TensorFormat.NHCWB16: |
| 971 | # Check that all BasePointer addresses are aligned to 16 bytes |
| 972 | assert (int(addresses[0]) % 16) == 0 |
| 973 | assert (int(addresses[1]) % 16) == 0 |
| 974 | assert (int(addresses[2]) % 16) == 0 |
| 975 | assert (int(addresses[3]) % 16) == 0 |
| 976 | |
| 977 | ofm_dtype = cmd.ofm_tensor.dtype |
| 978 | assert ofm_dtype.type & BaseType.Int |
| 979 | prec = 0 |
| 980 | if ofm_dtype.size_in_bits() == 8: |
| 981 | prec = 0 |
| 982 | elif ofm_dtype.size_in_bits() == 16: |
| 983 | prec = 2 |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 984 | elif ofm_dtype.size_in_bits() == 32: |
| 985 | prec = 4 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 986 | else: |
| 987 | assert 0 |
| 988 | |
| 989 | if ofm_dtype.type & BaseType.Signed: |
| 990 | prec += 1 |
| 991 | |
| 992 | if use_global_scale: |
| 993 | # Set global scale bit, as opposed to using per channel scale |
| 994 | prec |= 1 << 8 |
| 995 | |
| 996 | if cmd.ofm_tensor.format == TensorFormat.NHCWB16: |
| 997 | prec |= 1 << 6 |
| 998 | |
| 999 | prec |= rounding_mode.value << 14 |
| 1000 | |
| 1001 | emit.cmd0_with_param(cmd0.NPU_SET_OFM_PRECISION, prec) |
| 1002 | |
| 1003 | prec = None |
| 1004 | weight_bits = 8 |
| 1005 | if cmd.weight_tensor is not None: |
| 1006 | weight_bits = cmd.weight_tensor.dtype.size_in_bits() |
| 1007 | |
| 1008 | ifm_dtype = cmd.ifm_tensor.dtype |
| 1009 | |
| 1010 | assert weight_bits == 8, "Unsupported weight bit depth" |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 1011 | assert ( |
| 1012 | ifm_dtype.size_in_bits() in {8, 16} |
| 1013 | or ifm_dtype.size_in_bits() == 32 |
| 1014 | and npu_block_type in (NpuBlockType.ElementWise, NpuBlockType.ReduceSum) |
| 1015 | ), "Unsupported ifm bit depth" |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1016 | |
| 1017 | if ifm_dtype.size_in_bits() == 8: |
| 1018 | if ifm_dtype.type & BaseType.Signed: |
Diqing Zhong | fed918b | 2020-04-27 10:27:34 +0200 | [diff] [blame] | 1019 | prec = ifm_precision.S8 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1020 | else: |
Diqing Zhong | fed918b | 2020-04-27 10:27:34 +0200 | [diff] [blame] | 1021 | prec = ifm_precision.U8 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1022 | elif ifm_dtype.size_in_bits() == 16: |
| 1023 | if ifm_dtype.type & BaseType.Signed: |
Diqing Zhong | fed918b | 2020-04-27 10:27:34 +0200 | [diff] [blame] | 1024 | prec = ifm_precision.S16 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1025 | else: |
Diqing Zhong | fed918b | 2020-04-27 10:27:34 +0200 | [diff] [blame] | 1026 | prec = ifm_precision.U16 |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 1027 | elif ifm_dtype == DataType.int32: |
| 1028 | prec = ifm_precision.S32 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1029 | |
| 1030 | ifm_prec = prec.value |
| 1031 | ifm2_prec = ifm_prec |
| 1032 | |
| 1033 | if cmd.ifm_tensor.format == TensorFormat.NHCWB16: |
| 1034 | ifm_prec |= 1 << 6 |
| 1035 | |
| 1036 | ifm_prec |= op_to_scale << 8 |
| 1037 | |
| 1038 | emit.cmd0_with_param(cmd0.NPU_SET_IFM_PRECISION, ifm_prec) |
| 1039 | |
| 1040 | if cmd.ifm2_tensor is not None: |
| 1041 | if cmd.ifm2_tensor.format == TensorFormat.NHCWB16: |
| 1042 | ifm2_prec |= 1 << 6 |
| 1043 | emit.cmd0_with_param(cmd0.NPU_SET_IFM2_PRECISION, ifm2_prec) |
| 1044 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1045 | # Get op parameters |
| 1046 | cur_ifm_block_depth = get_op_ifmofm_block_depth(arch, cmd) |
| 1047 | cur_ofm_block = Block(ps.block_config[1], ps.block_config[0], ps.block_config[3]) |
| 1048 | cur_ofm_rect = get_op_ofm_rect(cmd) |
| 1049 | cur_ifm_rect = get_op_ifm_rect(cmd) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1050 | cur_padLT = get_op_padding_lt(cmd) |
| 1051 | if (prev_kernel is not None) and (cur_kernel is not None) and has_prev_op_dependency(prev_cmd, cmd): |
| 1052 | if cmd.ifm_tensor.shape == prev_cmd.ofm_tensor.shape: |
| 1053 | blockdep = arch.calc_block_dep( |
| 1054 | prev_ifm_rect, |
| 1055 | prev_ofm_rect, |
| 1056 | prev_ifm_block_depth, |
| 1057 | prev_ofm_block, |
| 1058 | prev_kernel, |
| 1059 | cur_ifm_rect, |
| 1060 | cur_ofm_rect, |
| 1061 | cur_ifm_block_depth, |
| 1062 | cur_ofm_block, |
| 1063 | cur_kernel, |
| 1064 | cur_padLT, |
| 1065 | ) |
| 1066 | else: |
| 1067 | blockdep = 0 |
| 1068 | else: |
| 1069 | blockdep = ArchitectureFeatures.MAX_BLOCKDEP |
| 1070 | |
| 1071 | # Set between every op (dependent or not) |
| 1072 | blockdep = min(blockdep, arch.max_blockdep) |
| 1073 | emit.cmd0_with_param(cmd0.NPU_SET_BLOCKDEP, blockdep) |
| 1074 | prev_cmd = cmd |
| 1075 | |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 1076 | emit_cmd_waits(cmd_waits) |
| 1077 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1078 | if npu_block_type == NpuBlockType.ConvolutionMxN: |
| 1079 | emit.cmd_do_operation(cmd0.NPU_OP_CONV) |
| 1080 | elif npu_block_type == NpuBlockType.ConvolutionDepthWise: |
| 1081 | emit.cmd_do_operation(cmd0.NPU_OP_DEPTHWISE) |
| 1082 | elif npu_block_type == NpuBlockType.VectorProduct: |
| 1083 | # Vector product is implemented using a 1x1 convolution |
| 1084 | emit.cmd_do_operation(cmd0.NPU_OP_CONV) |
| 1085 | elif npu_block_type == NpuBlockType.Pooling: |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 1086 | param = pooling_mode.MAX.value if primary_op.type.is_maxpool_op() else pooling_mode.AVERAGE.value |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1087 | emit.cmd_do_operation(cmd0.NPU_OP_POOL, param=param) |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 1088 | elif npu_block_type == NpuBlockType.ReduceSum: |
| 1089 | emit.cmd_do_operation(cmd0.NPU_OP_POOL, param=pooling_mode.REDUCE_SUM.value) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1090 | elif npu_block_type == NpuBlockType.ElementWise: |
| 1091 | param = elementwise_mode_map[primary_op.type] |
| 1092 | emit.cmd_do_operation(cmd0.NPU_OP_ELEMENTWISE, param) |
| 1093 | else: |
| 1094 | print("Warning: Skipping register command stream generation for", ps) |
| 1095 | |
| 1096 | # Fill in final part of command stream: |
| 1097 | emit.cmd_do_operation(cmd0.NPU_OP_STOP, param=0xFFFF) |
| 1098 | |
| 1099 | sg.register_command_stream = emit.to_list() |
| 1100 | if verbose: |
| 1101 | emit.print_cmds() |
| 1102 | print("number of commands", len(emit.cmd_stream)) |
| 1103 | print("command stream length in words", len(sg.register_command_stream)) |