alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | /* |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 2 | * Copyright (c) 2022 Arm Limited. All rights reserved. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 17 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 18 | #include "platform_drivers.h" |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 19 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 20 | #include "log_macros.h" /* Logging functions */ |
| 21 | #include "device_mps3.h" /* FPGA level definitions and functions. */ |
Kshitij Sisodia | acc6b85 | 2022-03-01 10:23:11 +0000 | [diff] [blame^] | 22 | #include "uart_stdout.h" /* stdout over UART. */ |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 23 | |
| 24 | #include <string.h> /* For strncpy */ |
| 25 | |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 26 | #if defined(ARM_NPU) |
| 27 | #include "ethosu_npu_init.h" |
| 28 | |
| 29 | #if defined(TIMING_ADAPTER_AVAILABLE) |
| 30 | #include "ethosu_ta_init.h" |
| 31 | #endif /* TIMING_ADAPTER_AVAILABLE */ |
| 32 | |
| 33 | #endif /* ARM_NPU */ |
| 34 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 35 | /** |
| 36 | * @brief Checks if the platform is valid by checking |
| 37 | * the CPU ID for the FPGA implementation against |
| 38 | * the register from the CPU core. |
| 39 | * @return 0 if successful, 1 otherwise |
| 40 | */ |
| 41 | static int verify_platform(void); |
| 42 | |
| 43 | int platform_init(void) |
| 44 | { |
| 45 | int err = 0; |
| 46 | |
| 47 | SystemCoreClockUpdate(); /* From start up code */ |
| 48 | |
| 49 | /* UART init - will enable valid use of printf (stdout |
| 50 | * re-directed at this UART (UART0) */ |
| 51 | UartStdOutInit(); |
| 52 | |
| 53 | if (0 != (err = verify_platform())) { |
| 54 | return err; |
| 55 | } |
| 56 | |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 57 | #if defined(ARM_NPU) |
| 58 | |
| 59 | #if defined(TIMING_ADAPTER_AVAILABLE) |
| 60 | /* If the platform has timing adapter blocks along with Ethos-U core |
| 61 | * block, initialise them here. */ |
| 62 | if (0 != (err = arm_ethosu_timing_adapter_init())) |
| 63 | { |
| 64 | return err; |
| 65 | } |
| 66 | #endif /* TIMING_ADAPTER_AVAILABLE */ |
| 67 | |
| 68 | int state; |
| 69 | |
| 70 | /* If Arm Ethos-U NPU is to be used, we initialise it here */ |
| 71 | if (0 != (state = arm_ethosu_npu_init())) |
| 72 | { |
| 73 | return state; |
| 74 | } |
| 75 | |
| 76 | #endif /* ARM_NPU */ |
| 77 | |
| 78 | /* Print target design info */ |
| 79 | info("Target system design: %s\n", DESIGN_NAME); |
| 80 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | void platform_release(void) |
| 85 | { |
| 86 | __disable_irq(); |
| 87 | } |
| 88 | |
| 89 | void platform_name(char* name, size_t size) |
| 90 | { |
| 91 | strncpy(name, DESIGN_NAME, size); |
| 92 | } |
| 93 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 94 | #define CREATE_MASK(msb, lsb) (int)(((1U << ((msb) - (lsb) + 1)) - 1) << (lsb)) |
| 95 | #define MASK_BITS(arg, msb, lsb) (int)((arg) & CREATE_MASK(msb, lsb)) |
| 96 | #define EXTRACT_BITS(arg, msb, lsb) (int)(MASK_BITS(arg, msb, lsb) >> (lsb)) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 97 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 98 | static int verify_platform(void) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 99 | { |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 100 | uint32_t id = 0; |
| 101 | uint32_t fpgaid = 0; |
| 102 | uint32_t apnote = 0; |
| 103 | uint32_t rev = 0; |
| 104 | uint32_t aid = 0; |
| 105 | uint32_t fpga_clk = 0; |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 106 | const uint32_t ascii_A = (uint32_t)('A'); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 107 | |
| 108 | /* Initialise the LEDs as the switches are */ |
| 109 | MPS3_FPGAIO->LED = MPS3_FPGAIO->SWITCHES & 0xFF; |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 110 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 111 | info("Processor internal clock: %" PRIu32 "Hz\n", GetMPS3CoreClock()); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 112 | |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 113 | /* Get revision information from various registers */ |
| 114 | rev = MPS3_SCC->CFG_REG4; |
| 115 | fpgaid = MPS3_SCC->SCC_ID; |
| 116 | aid = MPS3_SCC->SCC_AID; |
| 117 | apnote = EXTRACT_BITS(fpgaid, 15, 4); |
| 118 | fpga_clk = GetMPS3CoreClock(); |
| 119 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 120 | info("V2M-MPS3 revision %c\n\n", (char)(rev + ascii_A)); |
| 121 | info("Application Note AN%" PRIx32 ", Revision %c\n", apnote, |
| 122 | (char)(EXTRACT_BITS(aid, 23, 20) + ascii_A)); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 123 | info("MPS3 build %d\n", EXTRACT_BITS(aid, 31, 24)); |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 124 | info("MPS3 core clock has been set to: %" PRIu32 "Hz\n", fpga_clk); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 125 | |
| 126 | /* Display CPU ID */ |
| 127 | id = SCB->CPUID; |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 128 | info("CPU ID: 0x%08" PRIx32 "\n", id); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 129 | |
| 130 | if(EXTRACT_BITS(id, 15, 8) == 0xD2) { |
| 131 | if (EXTRACT_BITS(id, 7, 4) == 2) { |
| 132 | info ("CPU: Cortex-M55 r%dp%d\n\n", |
| 133 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 134 | #if defined (CPU_CORTEX_M55) |
| 135 | /* CPU ID should be "0x_41_0f_d2_20" for Cortex-M55 */ |
| 136 | return 0; |
| 137 | #endif /* CPU_CORTEX_M55 */ |
| 138 | } else if (EXTRACT_BITS(id, 7, 4) == 1) { |
| 139 | info ("CPU: Cortex-M33 r%dp%d\n\n", |
| 140 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 141 | #if defined (CPU_CORTEX_M33) |
| 142 | return 0; |
| 143 | #endif /* CPU_CORTEX_M33 */ |
| 144 | } else if (EXTRACT_BITS(id, 7, 4) == 0) { |
| 145 | info ("CPU: Cortex-M23 r%dp%d\n\n", |
| 146 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 147 | } else { |
| 148 | info ("CPU: Cortex-M processor family"); |
| 149 | } |
| 150 | } else if (EXTRACT_BITS(id, 15, 8) == 0xC6) { |
| 151 | info ("CPU: Cortex-M%d+ r%dp%d\n\n", |
| 152 | EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), |
| 153 | EXTRACT_BITS(id, 3, 0)); |
| 154 | } else { |
| 155 | info ("CPU: Cortex-M%d r%dp%d\n\n", |
| 156 | EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), |
| 157 | EXTRACT_BITS(id, 3, 0)); |
| 158 | } |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 159 | |
| 160 | /* If the CPU is anything other than M33 or M55, we return 1 */ |
| 161 | printf_err("CPU mismatch!\n"); |
| 162 | return 1; |
| 163 | } |