Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019-2020 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: Apache-2.0 |
| 5 | * |
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 7 | * not use this file except in compliance with the License. |
| 8 | * You may obtain a copy of the License at |
| 9 | * |
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
| 11 | * |
| 12 | * Unless required by applicable law or agreed to in writing, software |
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 15 | * See the License for the specific language governing permissions and |
| 16 | * limitations under the License. |
| 17 | */ |
| 18 | |
Kristofer Jonsson | 3c43917 | 2020-08-05 09:38:40 +0200 | [diff] [blame] | 19 | #ifndef ETHOSU_DEVICE_H |
| 20 | #define ETHOSU_DEVICE_H |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 21 | |
| 22 | /****************************************************************************** |
| 23 | * Includes |
| 24 | ******************************************************************************/ |
| 25 | |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 26 | #include <stdbool.h> |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 27 | #include <stdint.h> |
| 28 | |
| 29 | #ifdef __cplusplus |
| 30 | extern "C" { |
| 31 | #endif |
| 32 | |
| 33 | /****************************************************************************** |
| 34 | * Defines |
| 35 | ******************************************************************************/ |
| 36 | |
| 37 | #define ETHOSU_DRIVER_VERSION_MAJOR 0 ///< Driver major version |
Douglas Troha | f6a85da | 2020-05-11 11:45:28 +0200 | [diff] [blame] | 38 | #define ETHOSU_DRIVER_VERSION_MINOR 16 ///< Driver minor version |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 39 | #define ETHOSU_DRIVER_VERSION_PATCH 0 ///< Driver patch version |
| 40 | #define ETHOSU_DRIVER_BASEP_INDEXES 8 ///< Number of base pointer indexes |
| 41 | |
Anton Moberg | 61da4d3 | 2020-12-22 16:00:31 +0100 | [diff] [blame] | 42 | #ifndef ETHOSU_PMU_NCOUNTERS |
| 43 | #define ETHOSU_PMU_NCOUNTERS 4 |
| 44 | #endif |
| 45 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 46 | /****************************************************************************** |
| 47 | * Types |
| 48 | ******************************************************************************/ |
| 49 | |
| 50 | enum ethosu_error_codes |
| 51 | { |
| 52 | ETHOSU_SUCCESS = 0, ///< Success |
| 53 | ETHOSU_GENERIC_FAILURE = -1, ///< Generic failure |
| 54 | ETHOSU_INVALID_PARAM = -2 ///< Invalid parameter |
| 55 | }; |
| 56 | |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 57 | struct ethosu_device |
| 58 | { |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 59 | volatile uint32_t *base_address; |
Kristofer Jonsson | c6e7a1f | 2020-11-24 09:20:14 +0100 | [diff] [blame] | 60 | uint32_t proto; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 61 | uint32_t pmcr; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 62 | uint32_t pmccntr[2]; |
Kristofer Jonsson | ef387ea | 2020-08-25 16:32:21 +0200 | [diff] [blame] | 63 | uint32_t pmcnten; |
| 64 | uint32_t pmint; |
| 65 | uint32_t pmccntr_cfg; |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 66 | uint32_t pmu_evcntr[ETHOSU_PMU_NCOUNTERS]; |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 67 | uint32_t pmu_evtypr[ETHOSU_PMU_NCOUNTERS]; |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 68 | uint32_t secure; |
| 69 | uint32_t privileged; |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 70 | }; |
| 71 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 72 | struct ethosu_id |
| 73 | { |
| 74 | uint32_t version_status; ///< Version status |
| 75 | uint32_t version_minor; ///< Version minor |
| 76 | uint32_t version_major; ///< Version major |
| 77 | uint32_t product_major; ///< Product major |
| 78 | uint32_t arch_patch_rev; ///< Architecture version patch |
| 79 | uint32_t arch_minor_rev; ///< Architecture version minor |
| 80 | uint32_t arch_major_rev; ///< Architecture version major |
| 81 | }; |
| 82 | |
| 83 | struct ethosu_config |
| 84 | { |
| 85 | struct |
| 86 | { |
| 87 | uint32_t macs_per_cc; ///< MACs per clock cycle |
| 88 | uint32_t cmd_stream_version; ///< NPU command stream version |
| 89 | uint32_t shram_size; ///< SHRAM size |
| 90 | }; |
| 91 | }; |
| 92 | |
| 93 | /** |
| 94 | * Memory type parameter for set_regioncfg_reg: |
| 95 | * Counter{0,1}: Outstanding transactions for |
| 96 | * AXI port 0 for memory type/region a=0,b=1 |
| 97 | * Counter{2,3}: Outstanding transactions for |
| 98 | * AXI port 1 for memory type/region a=2,b=3 |
| 99 | */ |
| 100 | enum ethosu_memory_type |
| 101 | { |
| 102 | ETHOSU_AXI0_OUTSTANDING_COUNTER0 = 0, ///< NPU axi0_outstanding_counter0 |
| 103 | ETHOSU_AXI0_OUTSTANDING_COUNTER1 = 1, ///< NPU axi0_outstanding_counter1 |
| 104 | ETHOSU_AXI1_OUTSTANDING_COUNTER2 = 2, ///< NPU axi1_outstanding_counter2 |
| 105 | ETHOSU_AXI1_OUTSTANDING_COUNTER3 = 3 ///< NPU axi1_outstanding_counter3 |
| 106 | }; |
| 107 | |
| 108 | enum ethosu_axi_limit_beats |
| 109 | { |
| 110 | ETHOSU_AXI_LIMIT_64_BYTES = 0, ///< NPU AXI limit 64 byte burst split alignment. |
| 111 | ETHOSU_AXI_LIMIT_128_BYTES = 1, ///< NPU AXI limit 128 byte burst split alignment. |
| 112 | ETHOSU_AXI_LIMIT_256_BYTES = 2 ///< NPU AXI limit 256 byte burst split alignment. |
| 113 | }; |
| 114 | |
| 115 | enum ethosu_axi_limit_mem_type |
| 116 | { |
| 117 | ETHOSU_MEM_TYPE_DEVICE_NON_BUFFERABLE = 0, |
| 118 | ETHOSU_MEM_TYPE_DEVICE_BUFFERABLE = 1, |
| 119 | ETHOSU_MEM_TYPE_NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2, |
| 120 | ETHOSU_MEM_TYPE_NORMAL_NON_CACHEABLE_BUFFERABLE = 3, |
| 121 | ETHOSU_MEM_TYPE_WRITE_THROUGH_NO_ALLOCATE = 4, |
| 122 | ETHOSU_MEM_TYPE_WRITE_THROUGH_READ_ALLOCATE = 5, |
| 123 | ETHOSU_MEM_TYPE_WRITE_THROUGH_WRITE_ALLOCATE = 6, |
| 124 | ETHOSU_MEM_TYPE_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7, |
| 125 | ETHOSU_MEM_TYPE_WRITE_BACK_NO_ALLOCATE = 8, |
| 126 | ETHOSU_MEM_TYPE_WRITE_BACK_READ_ALLOCATE = 9, |
| 127 | ETHOSU_MEM_TYPE_WRITE_BACK_WRITE_ALLOCATE = 10, |
| 128 | ETHOSU_MEM_TYPE_WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11 |
| 129 | }; |
| 130 | |
| 131 | enum ethosu_clock_q_request |
| 132 | { |
| 133 | ETHOSU_CLOCK_Q_DISABLE = 0, ///< Disble NPU signal ready for clock off. |
| 134 | ETHOSU_CLOCK_Q_ENABLE = 1 ///< Enable NPU signal ready for clock off when stop+idle state reached. |
| 135 | }; |
| 136 | |
| 137 | enum ethosu_power_q_request |
| 138 | { |
| 139 | ETHOSU_POWER_Q_DISABLE = 0, ///< Disble NPU signal ready for power off. |
| 140 | ETHOSU_POWER_Q_ENABLE = 1 ///< Enable NPU signal ready for power off when stop+idle state reached. |
| 141 | }; |
| 142 | |
| 143 | /****************************************************************************** |
| 144 | * Prototypes |
| 145 | ******************************************************************************/ |
| 146 | |
| 147 | /** |
| 148 | * Initialize the device. |
| 149 | */ |
Per Åstrand | e6498f0 | 2020-11-09 15:33:12 +0100 | [diff] [blame] | 150 | enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev, |
| 151 | const void *base_address, |
| 152 | uint32_t secure_enable, |
| 153 | uint32_t privilege_enable); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 154 | |
| 155 | /** |
| 156 | * Get device id. |
| 157 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 158 | enum ethosu_error_codes ethosu_get_id(struct ethosu_device *dev, struct ethosu_id *id); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 159 | |
| 160 | /** |
| 161 | * Get device configuration. |
| 162 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 163 | enum ethosu_error_codes ethosu_get_config(struct ethosu_device *dev, struct ethosu_config *config); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 164 | |
| 165 | /** |
| 166 | * Execute a given command stream on NPU. |
| 167 | * \param[in] cmd_stream_ptr Pointer to the command stream |
| 168 | * \param[in] cms_length Command stream length |
| 169 | * \param[in] base_addr Pointer to array of base addresses |
| 170 | * - 0: weight tensor |
| 171 | * - 1: scratch tensor |
| 172 | * - All input tensors |
| 173 | * - All output tensors |
| 174 | * \param[in] num_base_addr Number of base addresses. |
| 175 | * \return \ref ethosu_error_codes |
| 176 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 177 | enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev, |
| 178 | const uint8_t *cmd_stream_ptr, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 179 | uint32_t cms_length, |
| 180 | const uint64_t *base_addr, |
| 181 | int num_base_addr); |
| 182 | |
| 183 | /** |
| 184 | * Check if IRQ is raised. |
| 185 | * \param[out] irq_status Pointer to IRQ status |
| 186 | * - 0 IRQ not raised |
| 187 | * - 1 IRQ raised |
| 188 | * \return \ref ethosu_error_codes |
| 189 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 190 | enum ethosu_error_codes ethosu_is_irq_raised(struct ethosu_device *dev, uint8_t *irq_status); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 191 | |
| 192 | /** |
| 193 | * Clear IRQ status. |
| 194 | * \return \ref ethosu_error_codes |
| 195 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 196 | enum ethosu_error_codes ethosu_clear_irq_status(struct ethosu_device *dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 197 | |
| 198 | /** |
| 199 | * Get the 16 bit status mask. |
| 200 | * \param[out] irq_status_mask Pointer to the status mask. |
| 201 | * The lower 16 bits of status reg are returned. |
| 202 | * bit0: state |
| 203 | * bit1: irq_raised |
| 204 | * bit2: bus_status |
| 205 | * bit3: reset_status |
| 206 | * bit4: cmd_parse_error |
| 207 | * bit5: cmd_end_reached |
| 208 | * bit6: pmu_irq_raised |
| 209 | * bit7-15: reserved |
| 210 | * \return \ref ethosu_error_codes |
| 211 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 212 | enum ethosu_error_codes ethosu_get_status_mask(struct ethosu_device *dev, uint16_t *status_mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 213 | |
| 214 | /** |
| 215 | * Get the 16 bit IRQ history mask. |
| 216 | * \param[out] irq_history_mask Pointer to the IRQ history mask. |
| 217 | * \return \ref ethosu_error_codes |
| 218 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 219 | enum ethosu_error_codes ethosu_get_irq_history_mask(struct ethosu_device *dev, uint16_t *irq_history_mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 220 | |
| 221 | /** |
| 222 | * Clear the given bits in the |
| 223 | * IRQ history mask. |
| 224 | * \param[in] irq_history_clear_mask 16 bit mask indicating which bits to |
| 225 | * clear in the IRQ history mask. |
| 226 | * \return \ref ethosu_error_codes |
| 227 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 228 | enum ethosu_error_codes ethosu_clear_irq_history_mask(struct ethosu_device *dev, uint16_t irq_history_clear_mask); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 229 | |
| 230 | /** |
| 231 | * Perform a NPU soft reset. |
| 232 | * \return \ref ethosu_error_codes |
| 233 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 234 | enum ethosu_error_codes ethosu_soft_reset(struct ethosu_device *dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 235 | |
| 236 | /** |
| 237 | * Wait for reset ready. |
| 238 | * \return \ref ethosu_error_codes |
| 239 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 240 | enum ethosu_error_codes ethosu_wait_for_reset(struct ethosu_device *dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 241 | |
| 242 | /** |
| 243 | * Read and return the content of a given NPU APB |
| 244 | * register range. |
| 245 | * \param[in] start_address Start address. |
| 246 | * \param[in] num_reg Number of registers to read. |
| 247 | * \param[out] reg_p Pointer to a output area, allocated by the |
| 248 | * caller, where the register content shall be |
| 249 | * written. |
| 250 | * \return \ref ethosu_error_codes |
| 251 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 252 | enum ethosu_error_codes ethosu_read_apb_reg(struct ethosu_device *dev, |
| 253 | uint32_t start_address, |
| 254 | uint16_t num_reg, |
| 255 | uint32_t *reg_p); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 256 | |
| 257 | /** |
| 258 | * Set qconfig register. I.e. |
| 259 | * AXI configuration for the command stream. |
| 260 | * \param[in] memory_type Memory_type to use for command stream: |
| 261 | * enum ethosu_memory_type. |
| 262 | * \return \ref ethosu_error_codes |
| 263 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 264 | enum ethosu_error_codes ethosu_set_qconfig(struct ethosu_device *dev, enum ethosu_memory_type memory_type); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 265 | |
| 266 | /** |
| 267 | * Set register REGIONCFG. |
| 268 | * Base pointer configuration. |
| 269 | * Bits[2*k+1:2*k] give the memory type for BASEP[k]. |
| 270 | * \param[in] region Region field to set: 0 - 7. |
| 271 | * \param[in] memory_type Memory_type to use for region: enum ethosu_memory_type. |
| 272 | * \return \ref ethosu_error_codes |
| 273 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 274 | enum ethosu_error_codes ethosu_set_regioncfg(struct ethosu_device *dev, |
| 275 | uint8_t region, |
| 276 | enum ethosu_memory_type memory_type); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 277 | |
| 278 | /** |
| 279 | * Set AXI limit parameters for port 0 counter 0. |
| 280 | * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats. |
| 281 | * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type |
| 282 | * \param[in] max_reads Maximum number of outstanding reads. |
| 283 | * \param[in] max_writes Maximum number of outstanding writes. |
| 284 | * \return \ref ethosu_error_codes |
| 285 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 286 | enum ethosu_error_codes ethosu_set_axi_limit0(struct ethosu_device *dev, |
| 287 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 288 | enum ethosu_axi_limit_mem_type memtype, |
| 289 | uint8_t max_reads, |
| 290 | uint8_t max_writes); |
| 291 | /** |
| 292 | * Set AXI limit parameters for port 0 counter 1. |
| 293 | * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats. |
| 294 | * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type |
| 295 | * \param[in] max_reads Maximum number of outstanding reads. |
| 296 | * \param[in] max_writes Maximum number of outstanding writes. |
| 297 | * \return \ref ethosu_error_codes |
| 298 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 299 | enum ethosu_error_codes ethosu_set_axi_limit1(struct ethosu_device *dev, |
| 300 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 301 | enum ethosu_axi_limit_mem_type memtype, |
| 302 | uint8_t max_reads, |
| 303 | uint8_t max_writes); |
| 304 | /** |
| 305 | * Set AXI limit parameters for port 1 counter 2. |
| 306 | * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats. |
| 307 | * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type |
| 308 | * \param[in] max_reads Maximum number of outstanding reads. |
| 309 | * \param[in] max_writes Maximum number of outstanding writes. |
| 310 | * \return \ref ethosu_error_codes |
| 311 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 312 | enum ethosu_error_codes ethosu_set_axi_limit2(struct ethosu_device *dev, |
| 313 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 314 | enum ethosu_axi_limit_mem_type memtype, |
| 315 | uint8_t max_reads, |
| 316 | uint8_t max_writes); |
| 317 | /** |
| 318 | * Set AXI limit parameters for port 1 counter 3. |
| 319 | * \param[in] max_beats Burst split alignment, \ref ethosu_axi_limit_beats. |
| 320 | * \param[in] memtype Cache policy \ref ethosu_axi_limit_mem_type |
| 321 | * \param[in] max_reads Maximum number of outstanding reads. |
| 322 | * \param[in] max_writes Maximum number of outstanding writes. |
| 323 | * \return \ref ethosu_error_codes |
| 324 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 325 | enum ethosu_error_codes ethosu_set_axi_limit3(struct ethosu_device *dev, |
| 326 | enum ethosu_axi_limit_beats max_beats, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 327 | enum ethosu_axi_limit_mem_type memtype, |
| 328 | uint8_t max_reads, |
| 329 | uint8_t max_writes); |
| 330 | |
| 331 | /** |
| 332 | * Get current command stream queue read position. |
| 333 | * \param[out] qread Pointer to queue read. |
| 334 | * \return \ref ethosu_error_codes |
| 335 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 336 | enum ethosu_error_codes ethosu_get_qread(struct ethosu_device *dev, uint32_t *qread); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 337 | |
| 338 | /** |
| 339 | * Get revision of NPU |
| 340 | * \param[out] revision Pointer to revision read. |
| 341 | * \return \ref ethosu_error_codes |
| 342 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 343 | enum ethosu_error_codes ethosu_get_revision(struct ethosu_device *dev, uint32_t *revision); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 344 | |
| 345 | /** |
| 346 | * Issue run command for the currently programmed |
| 347 | * command stream, starting at current queue read |
| 348 | * position. |
| 349 | * \return \ref ethosu_error_codes |
| 350 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 351 | enum ethosu_error_codes ethosu_set_command_run(struct ethosu_device *dev); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 352 | |
| 353 | /** |
| 354 | * Dump a 1KB section of SHRAM. |
| 355 | * \param[in] section Section offset to 1KB section in SHRAM. |
| 356 | * \param[out] shram_p Pointer to a output area, allocated by the |
| 357 | * caller, where the SHRAM content shall be |
| 358 | * written. |
| 359 | * \return \ref ethosu_error_codes |
| 360 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 361 | enum ethosu_error_codes ethosu_get_shram_data(struct ethosu_device *dev, int section, uint32_t *shram_p); |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 362 | |
| 363 | /** |
| 364 | * Set clock and power q request enable bits. |
| 365 | * \param[in] clock_q Clock q ENABLE/DISABLE \ref clock_q_request. |
| 366 | * \param[in] power_q Power q ENABLE/DISABLE \ref power_q_request. |
| 367 | * \return \ref ethosu_error_codes |
| 368 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 369 | enum ethosu_error_codes ethosu_set_clock_and_power(struct ethosu_device *dev, |
| 370 | enum ethosu_clock_q_request clock_q, |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 371 | enum ethosu_power_q_request power_q); |
| 372 | |
Kristofer Jonsson | 3c43917 | 2020-08-05 09:38:40 +0200 | [diff] [blame] | 373 | /** |
| 374 | * Read register. |
| 375 | * \param[in] address Address to read. |
| 376 | * \return Register value. |
| 377 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 378 | uint32_t ethosu_read_reg(struct ethosu_device *dev, uint32_t address); |
| 379 | |
Kristofer Jonsson | 3c43917 | 2020-08-05 09:38:40 +0200 | [diff] [blame] | 380 | /** |
| 381 | * Write register. |
| 382 | * \param[in] address Address to read. |
| 383 | * \param[in] value Value to be written. |
| 384 | */ |
Bhavik Patel | dae5be0 | 2020-06-18 15:25:15 +0200 | [diff] [blame] | 385 | void ethosu_write_reg(struct ethosu_device *dev, uint32_t address, uint32_t value); |
| 386 | |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 387 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 388 | * Write register with shadow variable. |
| 389 | * \param[in] address Address to read. |
| 390 | * \param[in] value Value to be written. |
| 391 | */ |
| 392 | void ethosu_write_reg_shadow(struct ethosu_device *dev, uint32_t address, uint32_t value, uint32_t *shadow); |
| 393 | |
| 394 | /** |
Bhavik Patel | 5da4092 | 2020-07-15 10:06:43 +0200 | [diff] [blame] | 395 | * Save the PMU configuration to ethosu_device struct. |
| 396 | * \param[in] dev Ethos-U device where the PMU configuration is |
| 397 | * saved. |
| 398 | * \return \ref ethosu_error_codes |
| 399 | */ |
| 400 | enum ethosu_error_codes ethosu_save_pmu_config(struct ethosu_device *dev); |
| 401 | |
| 402 | /** |
| 403 | * Restore the PMU configuration from a ethosu_device struct. |
| 404 | * \param[in] dev Ethos-U device where the PMU configuration is |
| 405 | * stored. |
| 406 | * \return \ref ethosu_error_codes |
| 407 | */ |
| 408 | enum ethosu_error_codes ethosu_restore_pmu_config(struct ethosu_device *dev); |
| 409 | |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 410 | /** |
Kristofer Jonsson | 4dc73dc | 2020-10-16 12:33:47 +0200 | [diff] [blame] | 411 | * Save PMU counters to shadow variables in memory. |
| 412 | * \param[in] dev Ethos-U device where the PMU configuration is |
| 413 | * stored. |
| 414 | * \return \ref ethosu_error_codes |
| 415 | */ |
| 416 | enum ethosu_error_codes ethosu_save_pmu_counters(struct ethosu_device *dev); |
| 417 | |
| 418 | /** |
Bhavik Patel | 5f8dad1 | 2020-09-30 09:06:52 +0200 | [diff] [blame] | 419 | * Check if the STATUS register has any error bits set or not. |
| 420 | * \param[in] dev Ethos-U device to check. |
| 421 | * \return true if any error bits set, |
| 422 | * false otherwise. |
| 423 | */ |
| 424 | bool ethosu_status_has_error(struct ethosu_device *dev); |
| 425 | |
Kristofer Jonsson | 49bdee8 | 2020-04-06 13:21:21 +0200 | [diff] [blame] | 426 | #ifdef __cplusplus |
| 427 | } |
| 428 | #endif |
Kristofer Jonsson | 3c43917 | 2020-08-05 09:38:40 +0200 | [diff] [blame] | 429 | |
| 430 | #endif // ETHOSU_DEVICE_H |