alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | /* |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame] | 2 | * Copyright (c) 2022 Arm Limited. All rights reserved. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | #include "timer_mps3.h" |
| 18 | |
alexander | 31ae9f0 | 2022-02-10 16:15:54 +0000 | [diff] [blame] | 19 | #include "log_macros.h" |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 20 | #include "device_mps3.h" |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame] | 21 | #include "smm_mps3.h" /* Memory map for MPS3. */ |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 22 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 23 | static uint64_t cpu_cycle_count = 0; /* 64-bit cpu cycle counter */ |
| 24 | |
| 25 | /** |
| 26 | * @brief Gets the system tick triggered cycle counter for the CPU. |
| 27 | * @return 64-bit counter value. |
| 28 | **/ |
| 29 | static uint64_t Get_SysTick_Cycle_Count(void); |
| 30 | |
| 31 | /** |
| 32 | * SysTick initialisation |
| 33 | */ |
| 34 | static int Init_SysTick(void); |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 35 | |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 36 | void timer_reset(void) |
| 37 | { |
| 38 | MPS3_FPGAIO->CLK1HZ = 0; |
| 39 | MPS3_FPGAIO->CLK100HZ = 0; |
| 40 | MPS3_FPGAIO->COUNTER = 0; |
| 41 | |
| 42 | if (0 != Init_SysTick()) { |
| 43 | printf_err("Failed to initialise system tick config\n"); |
| 44 | } |
| 45 | debug("system tick config ready\n"); |
| 46 | } |
| 47 | |
alexander | 31ae9f0 | 2022-02-10 16:15:54 +0000 | [diff] [blame] | 48 | base_time_counter get_time_counter(void) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 49 | { |
alexander | 31ae9f0 | 2022-02-10 16:15:54 +0000 | [diff] [blame] | 50 | base_time_counter t = { |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 51 | .counter_1Hz = MPS3_FPGAIO->CLK1HZ, |
| 52 | .counter_100Hz = MPS3_FPGAIO->CLK100HZ, |
| 53 | .counter_fpga = MPS3_FPGAIO->COUNTER, |
| 54 | .counter_systick = Get_SysTick_Cycle_Count() |
| 55 | }; |
Kshitij Sisodia | 3c8256d | 2021-05-24 16:12:40 +0100 | [diff] [blame] | 56 | debug("Timestamp:\n"); |
| 57 | debug("\tCounter 1 Hz: %" PRIu32 "\n", t.counter_1Hz); |
| 58 | debug("\tCounter 100 Hz: %" PRIu32 "\n", t.counter_100Hz); |
| 59 | debug("\tCounter FPGA: %" PRIu32 "\n", t.counter_fpga); |
| 60 | debug("\tCounter CPU: %" PRIu64 "\n", t.counter_systick); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 61 | return t; |
| 62 | } |
| 63 | |
| 64 | /** |
| 65 | * Please note, that there are no checks for overflow in this function => if |
| 66 | * the time elapsed has been big (in days) this could happen and is currently |
| 67 | * not handled. |
| 68 | **/ |
alexander | 31ae9f0 | 2022-02-10 16:15:54 +0000 | [diff] [blame] | 69 | uint32_t get_duration_milliseconds(base_time_counter *start, |
| 70 | base_time_counter *end) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 71 | { |
| 72 | uint32_t time_elapsed = 0; |
| 73 | if (end->counter_100Hz > start->counter_100Hz) { |
| 74 | time_elapsed = (end->counter_100Hz - start->counter_100Hz) * 10; |
| 75 | } else { |
| 76 | time_elapsed = (end->counter_1Hz - start->counter_1Hz) * 1000 + |
| 77 | ((0xFFFFFFFF - start->counter_100Hz) + end->counter_100Hz + 1) * 10; |
| 78 | } |
| 79 | |
| 80 | /* If the time elapsed is less than 100ms, use microseconds count to be |
| 81 | * more precise */ |
| 82 | if (time_elapsed < 100) { |
| 83 | debug("Using the microsecond function instead..\n"); |
| 84 | return get_duration_microseconds(start, end)/1000; |
| 85 | } |
| 86 | |
| 87 | return time_elapsed; |
| 88 | } |
| 89 | |
| 90 | /** |
| 91 | * Like the microsecond counterpart, this function could return wrong results when |
| 92 | * the counter (MAINCLK) overflows. There are no overflow counters available. |
| 93 | **/ |
alexander | 31ae9f0 | 2022-02-10 16:15:54 +0000 | [diff] [blame] | 94 | uint32_t get_duration_microseconds(base_time_counter *start, |
| 95 | base_time_counter *end) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 96 | { |
| 97 | const int divisor = GetMPS3CoreClock()/1000000; |
| 98 | uint32_t time_elapsed = 0; |
| 99 | if (end->counter_fpga > start->counter_fpga) { |
| 100 | time_elapsed = (end->counter_fpga - start->counter_fpga)/divisor; |
| 101 | } else { |
| 102 | time_elapsed = ((0xFFFFFFFF - end->counter_fpga) |
| 103 | + start->counter_fpga + 1)/divisor; |
| 104 | } |
| 105 | return time_elapsed; |
| 106 | } |
| 107 | |
alexander | 31ae9f0 | 2022-02-10 16:15:54 +0000 | [diff] [blame] | 108 | uint64_t get_cycle_count_diff(base_time_counter *start, |
| 109 | base_time_counter *end) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 110 | { |
| 111 | if (start->counter_systick > end->counter_systick) { |
| 112 | warn("start > end; counter might have overflown\n"); |
| 113 | } |
| 114 | return end->counter_systick - start->counter_systick; |
| 115 | } |
| 116 | |
| 117 | void start_cycle_counter(void) |
| 118 | { |
| 119 | /* Nothing to do for FPGA */ |
| 120 | } |
| 121 | |
| 122 | void stop_cycle_counter(void) |
| 123 | { |
| 124 | /* Nothing to do for FPGA */ |
| 125 | } |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 126 | |
| 127 | void SysTick_Handler(void) |
| 128 | { |
| 129 | /* Increment the cycle counter based on load value. */ |
| 130 | cpu_cycle_count += SysTick->LOAD + 1; |
| 131 | } |
| 132 | |
| 133 | /** |
| 134 | * Gets the current SysTick derived counter value |
| 135 | */ |
| 136 | static uint64_t Get_SysTick_Cycle_Count(void) |
| 137 | { |
| 138 | uint32_t systick_val; |
| 139 | |
| 140 | NVIC_DisableIRQ(SysTick_IRQn); |
| 141 | systick_val = SysTick->VAL & SysTick_VAL_CURRENT_Msk; |
| 142 | NVIC_EnableIRQ(SysTick_IRQn); |
| 143 | |
| 144 | return cpu_cycle_count + (SysTick->LOAD - systick_val); |
| 145 | } |
| 146 | |
| 147 | /** |
| 148 | * SysTick initialisation |
| 149 | */ |
| 150 | static int Init_SysTick(void) |
| 151 | { |
| 152 | const uint32_t ticks_10ms = GetMPS3CoreClock()/100 + 1; |
| 153 | int err = 0; |
| 154 | |
| 155 | /* Reset CPU cycle count value. */ |
| 156 | cpu_cycle_count = 0; |
| 157 | |
| 158 | /* Changing configuration for sys tick => guard from being |
| 159 | * interrupted. */ |
| 160 | NVIC_DisableIRQ(SysTick_IRQn); |
| 161 | |
| 162 | /* SysTick init - this will enable interrupt too. */ |
| 163 | err = SysTick_Config(ticks_10ms); |
| 164 | |
| 165 | /* Enable interrupt again. */ |
| 166 | NVIC_EnableIRQ(SysTick_IRQn); |
| 167 | |
| 168 | /* Wait for SysTick to kick off */ |
| 169 | while (!err && !SysTick->VAL) { |
| 170 | __NOP(); |
| 171 | } |
| 172 | |
| 173 | return err; |
| 174 | } |