blob: 25e196a6fae16af5fb7ba8420391dc1120bdf3d7 [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +00001/*
Richard Burtonf32a86a2022-11-15 11:46:11 +00002 * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
alexander3c798932021-03-26 21:42:19 +00003 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17#include "timer_mps3.h"
18
alexander31ae9f02022-02-10 16:15:54 +000019#include "log_macros.h"
Kshitij Sisodiad5679cc2022-03-03 16:30:07 +000020#include "smm_mps3.h" /* Memory map for MPS3. */
alexander3c798932021-03-26 21:42:19 +000021
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +000022static uint64_t cpu_cycle_count = 0; /* 64-bit cpu cycle counter */
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010023static const char* unit_cycles = "cycles";
24static const char* unit_ms = "milliseconds";
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +000025
26/**
27 * @brief Gets the system tick triggered cycle counter for the CPU.
28 * @return 64-bit counter value.
29 **/
30static uint64_t Get_SysTick_Cycle_Count(void);
31
32/**
33 * SysTick initialisation
34 */
35static int Init_SysTick(void);
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010036
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010037/**
38 * @brief Adds one PMU counter to the counters' array
39 * @param value Value of the counter
40 * @param name Name for the given counter
41 * @param unit Unit for the "value"
42 * @param counters Pointer to the counter struct - the one to be populated.
43 * @return true if successfully added, false otherwise
44 */
45static bool add_pmu_counter(
46 uint64_t value,
47 const char* name,
48 const char* unit,
49 pmu_counters* counters);
50
51/**
52 * @brief Gets the evaluated millisecond timestamp from the given MPS3 counter struct.
53 * @param mps3_counters Pointer to the MPS3 counters.
54 * @return microseconds timestamp as 32 bit unsigned integer.
55 */
56static uint32_t get_tstamp_milliseconds(mps3_pmu_counters* mps3_counters);
57
58void platform_reset_counters(void)
alexander3c798932021-03-26 21:42:19 +000059{
60 MPS3_FPGAIO->CLK1HZ = 0;
61 MPS3_FPGAIO->CLK100HZ = 0;
62 MPS3_FPGAIO->COUNTER = 0;
63
64 if (0 != Init_SysTick()) {
65 printf_err("Failed to initialise system tick config\n");
66 }
67 debug("system tick config ready\n");
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010068
69#if defined (ARM_NPU)
70 ethosu_pmu_init();
71#endif /* defined (ARM_NPU) */
alexander3c798932021-03-26 21:42:19 +000072}
73
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010074void platform_get_counters(pmu_counters* counters)
alexander3c798932021-03-26 21:42:19 +000075{
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010076 counters->num_counters = 0;
77 counters->initialised = true;
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010078 uint32_t i = 0;
79
80#if defined (ARM_NPU)
81 ethosu_pmu_counters npu_counters = ethosu_get_pmu_counters();
82 for (i = 0; i < ETHOSU_PMU_NCOUNTERS; ++i) {
83 add_pmu_counter(
84 npu_counters.npu_evt_counters[i].counter_value,
85 npu_counters.npu_evt_counters[i].name,
86 npu_counters.npu_evt_counters[i].unit,
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010087 counters);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010088 }
89 for (i = 0; i < ETHOSU_DERIVED_NCOUNTERS; ++i) {
90 add_pmu_counter(
91 npu_counters.npu_derived_counters[i].counter_value,
92 npu_counters.npu_derived_counters[i].name,
93 npu_counters.npu_derived_counters[i].unit,
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010094 counters);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +010095 }
96 add_pmu_counter(
97 npu_counters.npu_total_ccnt,
98 "NPU TOTAL",
Kshitij Sisodia4cc40212022-04-08 09:54:53 +010099 unit_cycles,
100 counters);
Kshitij Sisodiaea8ce562022-04-12 11:10:11 +0100101#else
102 UNUSED(i);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100103#endif /* defined (ARM_NPU) */
104
105#if defined(CPU_PROFILE_ENABLED)
106 mps3_pmu_counters mps3_counters = {
107 .counter_1Hz = MPS3_FPGAIO->CLK1HZ,
108 .counter_100Hz = MPS3_FPGAIO->CLK100HZ,
109 .counter_fpga = MPS3_FPGAIO->COUNTER,
110 .counter_systick = Get_SysTick_Cycle_Count()
111 };
112
113 add_pmu_counter(
114 mps3_counters.counter_systick,
115 "CPU TOTAL",
Kshitij Sisodia4cc40212022-04-08 09:54:53 +0100116 unit_cycles,
117 counters);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100118
119 add_pmu_counter(
120 get_tstamp_milliseconds(&mps3_counters),
121 "DURATION",
Kshitij Sisodia4cc40212022-04-08 09:54:53 +0100122 unit_ms,
123 counters);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100124#endif /* defined(CPU_PROFILE_ENABLED) */
125
126#if !defined(CPU_PROFILE_ENABLED)
127 UNUSED(get_tstamp_milliseconds);
128 UNUSED(Get_SysTick_Cycle_Count);
Kshitij Sisodiab1904b12022-04-21 09:48:10 +0100129 UNUSED(unit_ms);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100130#if !defined(ARM_NPU)
Kshitij Sisodiab1904b12022-04-21 09:48:10 +0100131 UNUSED(unit_cycles);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100132 UNUSED(add_pmu_counter);
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100133#endif /* !defined(ARM_NPU) */
134#endif /* !defined(CPU_PROFILE_ENABLED) */
alexander3c798932021-03-26 21:42:19 +0000135}
136
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100137uint32_t get_mps3_core_clock(void)
alexander3c798932021-03-26 21:42:19 +0000138{
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100139 const uint32_t default_clock = 32000000 /* 32 MHz clock */;
140 static int warned_once = 0;
141 if (0 != MPS3_SCC->CFG_ACLK) {
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100142 return MPS3_SCC->CFG_ACLK;
alexander3c798932021-03-26 21:42:19 +0000143 }
144
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100145 if (!warned_once) {
146 warn("MPS3_SCC->CFG_ACLK reads 0. Assuming default clock of %" PRIu32 "\n",
147 default_clock);
148 warned_once = 1;
alexander3c798932021-03-26 21:42:19 +0000149 }
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100150 return default_clock;
alexander3c798932021-03-26 21:42:19 +0000151}
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +0000152
153void SysTick_Handler(void)
154{
155 /* Increment the cycle counter based on load value. */
156 cpu_cycle_count += SysTick->LOAD + 1;
157}
158
159/**
160 * Gets the current SysTick derived counter value
161 */
162static uint64_t Get_SysTick_Cycle_Count(void)
163{
164 uint32_t systick_val;
165
166 NVIC_DisableIRQ(SysTick_IRQn);
167 systick_val = SysTick->VAL & SysTick_VAL_CURRENT_Msk;
168 NVIC_EnableIRQ(SysTick_IRQn);
169
170 return cpu_cycle_count + (SysTick->LOAD - systick_val);
171}
172
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000173
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +0000174/**
175 * SysTick initialisation
176 */
177static int Init_SysTick(void)
178{
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000179 const uint32_t ticks_10ms = get_mps3_core_clock()/100 + 1;
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +0000180 int err = 0;
181
182 /* Reset CPU cycle count value. */
183 cpu_cycle_count = 0;
184
185 /* Changing configuration for sys tick => guard from being
186 * interrupted. */
187 NVIC_DisableIRQ(SysTick_IRQn);
188
189 /* SysTick init - this will enable interrupt too. */
190 err = SysTick_Config(ticks_10ms);
191
192 /* Enable interrupt again. */
193 NVIC_EnableIRQ(SysTick_IRQn);
194
195 /* Wait for SysTick to kick off */
196 while (!err && !SysTick->VAL) {
197 __NOP();
198 }
199
200 return err;
201}
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000202
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100203static bool add_pmu_counter(uint64_t value,
204 const char* name,
205 const char* unit,
206 pmu_counters* counters)
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000207{
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100208 const uint32_t idx = counters->num_counters;
209 if (idx < NUM_PMU_COUNTERS) {
210 counters->counters[idx].value = value;
211 counters->counters[idx].name = name;
212 counters->counters[idx].unit = unit;
213 ++counters->num_counters;
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000214
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100215 debug("%s: %" PRIu64 " %s\n", name, value, unit);
216 return true;
Kshitij Sisodiac22e80e2022-03-14 09:26:48 +0000217 }
Kshitij Sisodiada2ec062022-04-01 14:43:53 +0100218 printf_err("Failed to add PMU counter!\n");
219 return false;
220}
221
222static uint32_t get_tstamp_milliseconds(mps3_pmu_counters* mps3_counters)
223{
224 const uint32_t divisor = get_mps3_core_clock() / 1000;
225 if (mps3_counters->counter_100Hz > 100) {
226 return (mps3_counters->counter_100Hz * 10);
227 }
228 return (mps3_counters->counter_systick/divisor);
229}